Functions
6-2097SA6 Manual
C53000-G1176-C133-1
Figure 6-106 Logic diagram of the overvoltage protection for the positive sequence
voltage system
Overvoltage
Negative Sequence
System U
2
The device calculates the negative sequence system voltages according to its defining
equation:
U
2
=
1
/
3
⋅(U
L1
+ a
2
⋅U
L2
+ a⋅U
L3
)
with a
= e
j120°
.
The resulting single–phase AC voltage is fed to the two threshold stages 8! and
8!!. The logic is designed just like in the positive sequence system (Figure 6-106).
Combined with the associated time delays 78! and 78!! these stages form a
two-stage overvoltage protection for the negative sequence system. Here too, the
drop-off to pick-up ratio can be set. The overvoltage protection for the negative
sequence system can also be blocked via a binary input “!8!!%/.”. The stages
of the negative sequence voltage protection are automatically blocked as soon as an
asymmetrical voltage failure was detected (“Fuse–Failure–Monitor”, also see Section
6.19.1.3, margin heading “Fuse Failure Monitor (Non-Symmetrical Voltages)”) or
when the trip of the mcb for voltage transformers has been signalled via the binary
input “!)$,/)HHGHU97” (internal indication “internal blocking”).
The stages of the negative sequence voltage protection are automatically blocked
(with the internal automatic reclosure function) during single-pole automatic reclose
dead time, to avoid pick-up with the false negative sequence values arising during this
state. If the device cooperates with an external automatic reclosure function, or if a
single-pole tripping can be triggered by a different protection system (working in
parallel), the overvoltage protection for the negative sequence system must be
blocked via a binary input during single-pole tripping.
Overvoltage
Zero Sequence
System 3⋅U
0
Figure 6-107 depicts the logic diagram of the zero sequence voltage stage. The
fundamental frequency is numerically filtered from the measuring voltage so that the
harmonics or transient voltage peaks remain largely harmless.
The triple zero sequence voltage 3 U
0
is fed to the two threshold stages 8! and
8!!. Combined with the associated time delays 78! and 78!! these
stages form a two-stage overvoltage protection for the zero sequence system. Here
too, the drop-off to pick-up ratio can be set (8!!5(6(7).
The overvoltage protection for the zero voltage system can also be blocked via a
binary input “!8!!%/.”. The stages of the zero sequence voltage protection
are automatically blocked as soon as a asymmetrical voltage failure is detected
(“Fuse–Failure–Monitor”, also see Section 6.19.1.3, margin heading “Fuse Failure
Monitor (Non-Symmetrical Voltages)”) or if the trip of the mcb for voltage transformers
U
L3-E
U
L2-E
U
L1-E
U>
8!
T0
78!
T U1> TimeOut
U1> Pickup
U>>
8!!5(6(7
T0
78!!
T U1>> TimeOut
U1>> Pickup
U1>(>) TRIP
≥1
8!!
>U1>(>) BLK
U
1
U
Ph–E
FNo 10204
FNo 10280
FNo 10282
FNo 10284
FNo 10283
FNo 10281
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