Index
Index-7
control registers (IFR, IER, DBGIER) 2-14
data log interrupt (DLOGINT) 3-6, 7-27
effect on instructions in pipeline 4-4
general purpose 3-6
handling information by emulation
mode and state 7-13
INT1−INT14 3-6
maskable 3-6
definition 3-2
flow chart of operation 3-12
NMI 3-21
nonmaskable 3-17
definition 3-2
operation
overview 3-2
real-time mode 7-9
standard 3-11
stop mode 7-7
overview 3-2
real-time operating system interrupt (RTO-
SINT) 3-6
special cases, clearing IFR flag bit after TRAP
instruction 3-7, 3-8
time-critical 7-6
serviced in real-time mode 7-9
vectors 3-4
INTM C-11
INTR INTx 6-114
INTR instruction 3-17, D-10
IRET 6-116
IRET instruction 7-15, F-5
J
JTAG, signals 7-3
JTAG header to interface a target to the scan con-
troller, figure 7-3
JTAG port 7-1
L
LACL dma D-15
LB *XAR7 6-119
LB 22bit 6-120
LC *XAR7 6-121
LC 22bit 6-122
LCR #22bit 6-123
LCR *XARn 6-124
load auxiliary register 6-160
load AX 6-161
load data page pointer 6-162
load the interrupt enable register 6-163
load the overflow counter 6-176
loc16 5-2
loc32 5-2
logical shift left 6-133
logical shift right 6-140
long call using RPC 6-123
long indirect branch 6-119
long indirect call 6-121
long return 6-130
LOOP C-9
LOOP bit 2-35
Loop instruction status bit C-9
loop instruction status bit (LOOP) 2-35
loop while not zero 6-125
LOOPNZ loc16,#16bit 6-125
LOOPZ loc16,#16bit 6-127
LPADDR 6-129
LRET 6-130
LRETE 6-131
LRETER 6-132
LSL ACC,#1..16 6-133
LSL ACC,T 6-134
LSL AX,#1016 6-135
LSL AX,T 6-136
LSL64 ACC:P,#1..16 6-137
LSL64 ACC:P,T 6-138
LSLL ACC,T 6-139
LSR AX,#1016 6-140
LSR AX,T 6-141
LSR64 ACC:P,#1..16 6-142
LSR64 ACC:P,T 6-143
LSRL ACC,T 6-144
M
M0 M1 map bit C-9
M0M1MAP C-9, F-4
MAC P,loc16,0:pma 6-145
MAC P, loc16, *XAR7 6-147
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