YASKAWA SVC - Execution Flow for Slave CPU Synchronization

6.6 Slave CPU Synchronization
6.6.5 Execution Flow for Slave CPU Synchronization
6-25
6
Other Useful Functions
Slave I/O Register Configuration
6.6.5 Execution Flow for Slave CPU Synchronization
Refer to the following section for details on register areas.
Detailed Information When an SVC Function Module Is Set as a Slave (page 7-16)
Output Registers Input Registers
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
OW
Reserved for system.
IW
Reserved for system.
OW+1
Command Control
IW+1
Command Status
OW+2 Output Data 1 Low IW+2 Input Data 1 Low
High High
OW+3 Output Data 2 Low IW+3 Input Data 2 Low
High High
OW+4 Output Data 3 Low IW+4 Input Data 3 Low
High High
OW+5 Output Data 4 Low IW+5 Input Data 4 Low
High High
OW+6 Output Data 5 Low IW+6 Input Data 5 Low
High High
OW+7 Output Data 6 Low IW+7 Input Data 6 Low
High High






Information
Power ON to Master
Conrmation of Completion
of Slave Startup
Power ON to Slave
Operations on Master
Operations on Slave
SLVSC Control
Bit Turned ON
SLVSC Control
Bit Turned OFF
Conrmation That the Slave
CPU Is Synchronized
Conrmation That the Slave
CPU Is Synchronized
Conrmation of Completion of Slave
CPU Synchronization Preparations
Confirmation That the
Slave CPU Is Synchro-
nized (page 6-26)
Procedure to Turn ON Power
(page 6-26)