YASKAWA SVC - 11.3.5 Command Control; 11.3.6 Master Status

11.3 MECHATROLINK-III I/O Module Settings
11.3.5 Command Control
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11.3.5 Command Control
This section describes the details of the Command Control register.
 ALM_CLR: Clear Communications Alarm/Warning
• Definition
1: Clear alarms/warnings.
0: Disable clearing alarms/warnings.
• Description
The current alarms/warnings are cleared on the rising edge of this bit.
The same processing is performed for as the Clear Alarms/Warnings I/O command.
11.3.6 Master Status
This section describes the details of the Master Status register.
 TIMEOUT
• Definition
1: Command timeout detected.
0: Any state other than the above
• Description
This bit shows when execution of an I/O command is not completed within a specific period
of time (5 s).
Clear the alarm to restore operation.

CYCLIC_INIT_ERR
• Definition
1: Cyclic communications initialization incomplete state detected.
0: Any state other than the above
• Description
This bit shows when the I/O Module fails to initialize cyclic communications.
Clear the alarm to restore operation.

STATUS
• Definition
• Description
These bits show the internal state of the I/O communications driver.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserve ALM_CLR Reserve
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reserve
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STATUS
CYCLIC_
INIT_ERR
Reserve TIMEOUT
Value Meaning
0 hex Phase 0: The power supply is ON.
1 hex Phase 1: Status is initialized.
2 hex Phase 2: Communications are not synchronized.
3 hex Phase 3: Communications are synchronized.
4 hex Phase 4: Communications are stopped.
5 hex Phase 5: The power supply is OFF.