YASKAWA SVC - Page 454

7.2 MECHATROLINK Communications Settings
7.2.2 MECHATROLINK Detail Definition Dialog Box Details
7-18
 Output Register Configuration
 Command Control
This section describes the details of the Command Control register.
• SLVSC
• Definition
1: Restarting prohibited.
0: Restarting allowed.
• Description
Specify whether slave CPU synchronization is automatically restarted when the slave CPU
changes from synchronized to asynchronized status.
If SLVSC is set to 1, slave CPU synchronization will not be restarted when the slave CPU
changes from synchronized to asynchronized status and operation will be continued in asyn-
chronized status
If SLVSC is set to 0, slave CPU synchronization is automatically restarted when the slave CPU
changes from synchronized to asynchronized status.
Refer to the following section for details on slave CPU synchronization.
6.6 Slave CPU Synchronization on page 6-18
MECHATROLINK
Transmission Path
Output Registers
for Slave
(SVC or SVC32)
Master
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
00 hex RCMD OW+0
Reserved for system.
01 hex RWDT
02 hex
CMD_STAT
OW+1
Command Status
03 hex
04 hex Data 1 Low OW+2 Data 1 Low
05 hex High High
06 hex Data 2 Low OW+3 Data 2 Low
07 hex High High
08 hex Data 3 Low OW+4 Data 3 Low
09 hex High High
0A hex Data 4 Low OW+5 Data 4 Low
0B hex High High
0C hex Data 5 Low OW+6 Data 5 Low
0D hex High High
0E hex Data 6 Low OW+7 Data 6 Low
0F hex High High






Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved SLVSC
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reserved