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Abov A96G166 User Manual

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11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual
104
T1CRH (Timer 1 Control High Register): BBH
7
6
5
4
3
2
1
0
T1EN
T1BEN
T1MS1
T1MS0
T1PE
T1CC
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
T1EN
Control Timer 1
0
Timer 1 disable
1
Timer 1 enable (Counter clear and start)
T1BEN
Control Complementary PWM
0
Complementary PWM disable
1
Complementary PWM enable
T1MS[1:0]
Control Timer 1 Operation Mode
T1MS1
T1MS0
Description
0
0
Timer/counter mode (T1O: toggle at A match)
0
1
Capture mode (The A match interrupt can
occur)
1
0
PPG one-shot mode (PWM1O)
1
1
PPG repeat mode (PWM1O)
T1PE
Control Timer 1 port output
0
Timer 1 output disable
1
Timer 1 output enable
T1CC
Clear Timer 1 Counter
0
No effect
1
Clear the Timer 1 counter (When write, automatically
cleared “0” after being cleared counter)
T1CRL (Timer 1 Control Low Register): BAH
7
6
5
4
3
2
1
0
T1CK2
T1CK1
T1CK0
T1IFR
T1BPOL
T1POL
T1ECE
T1CNTR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
T1CK[2:0]
Select Timer 1 clock source. fx is main system clock frequency
T1CK2
T1CK1
T1CK0
Description
0
0
0
fx/2048
0
0
1
fx/64
0
1
0
fx/8
0
1
1
fx/4
1
0
0
fx/2
1
0
1
fx/1
1
1
0
HSI Direct (32MHz)
1
1
1
External clock (EC1)
T1IFR
When T1 Interrupt occurs, this bit becomes 1. For clearing bit, write 0
to this bit or auto clear by INT_ACK signal. Writing 1 has no effect.
0
T1 Interrupt no generation
1
T1 Interrupt generation
T1BPOL
PWM1OB Polarity Selection
0
Start High (PWM1OB is low level at disable)
1
Start Low (PWM1OB is high level at disable)
T1POL
T1O/PWM1O Polarity Selection
0
Start High (T1O/PWM1O is low level at disable)
1
Start Low (T1O/PWM1O is high level at disable)
T1ECE
Timer 1 External Clock Edge Selection
0
External clock falling edge
1
External clock rising edge
T1CNTR
Timer 1 Counter Read Control
0
No effect
1
Load the counter value to the B data register (When write,
automatically cleared 0 after being loaded)

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Abov A96G166 Specifications

General IconGeneral
BrandAbov
ModelA96G166
CategoryComputer Hardware
LanguageEnglish

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