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15. USART 0/1 A96G166/A96A166/A96S166 User’s manual

148

15.9 SPI mode

The USARTn can be set to operate in industrial standard SPI compliant mode. The SPI mode has the

following features.

 Full duplex, three-wire synchronous data transfer

 Master or Slave operation

 Supports all four SPI modes of operation (mode0, 1, 2, and 3)

 Selectable LSB first or MSB first data transfer

 Double buffered transmit and receive

 Programmable transmit bit rate

When the SPI mode is enabled (UMSEL[1:0]=3), the Slave Select (SSn) pin becomes active low input

in slave mode operation, or can be output in master mode operation if SPISS bit is set.

NOTE: That during SPI mode of operation, the pin RXDn is renamed as MISOn and TXDn is renamed as

MOSIn for compatibility to other SPI devices.

15.9.1 SPI clock formats and timing

To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the

USART has a clock polarity bit (UCPOL) and a clock phase control bit (UCPHA) to select one of four

clock formats for data transfers. UCPOL selectively insert an inverter in series with the clock. UCPHA

selects one of two different clock phase relationships between the clock and data. Note that UCPHA

and UCPOL bits in UnCTRL1 register have different meanings according to the UMSEL[1:0] bits

which decides the operating mode of USARTn.

Table 26 shows four combinations of UCPOL and UCPHA for SPI mode 0, 1, 2, and 3.

Table 26. CPOL Functionality

SPI Mode

UCPOL

UCPHA

Leading Edge

Trailing Edge

Sample (Rising)

Setup (Falling)

Setup (Rising)

Sample (Falling)

Setup (Rising)

Setup (Falling)

Sample (Rising)

Abov A96G166 User Manual

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