Abov A96G166 - Figure 77. SPI Clock Formats When UCPHA = 0

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A96G166/A96A166/A96S166 User’s manual 15. USART 0/1

149

Figure 77. SPI Clock Formats when UCPHA = 0

When UCPHA=0, the slave begins to drive its MISOn output with the first data bit value when SSn

goes to active low. The first XCKn edge causes both the master and the slave to sample the data bit

value on their MISOn and MOSIn inputs, respectively.

At the second XCKn edge, the USARTn shifts the second data bit value out to the MOSIn and MISOn

outputs of the master and slave, respectively. Unlike the case of UCPHA=1, when UCPHA=0, the

slave’s SSn input must go to its inactive high level between transfers. This is because the slave can

prepare the first data bit when it detects falling edge of SSn input.

XCKn

(UCPOL=1)

MISOn

MOSIn

XCKn

(UCPOL=0)

/SSn OUT

(MASTER)

BIT7

BIT0

/SSn IN

(SLAVE)

BIT6

BIT1

…

BIT2

BIT5

BIT0

BIT7

BIT1

BIT6

SAMPLE

MSB First

LSB First

Main Page

Introduction1
Reference Document1
Table of Contents2
Description12
Device Overview12
Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts12
Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts (Continued)13
A96G166/A96A166/A96S166 Block Diagram14
Figure 1. A96G166/A96A166/A96S166 Block Diagram14
Pinouts and Pin Description15
Pinouts15
Figure 2. A96G166 16SOPN Pin Assignment15
Figure 3. A96G166 20TSSOP/20SOP Pin Assignment16
Figure 4 A96A166 20SOP Pin Assignment16
Figure 5. A96S166 20TSSOP Pin Assignment17
Figure 6. A96G166 20 QFN Pin Assignment18
Figure 7. A96G166 28SOP Pin Assignment19
Figure 8. A96G166 32 LQFP Pin Assignment19
Pin Description20
Table 2. Normal Pin Description20
Table 2. Normal Pin Description (Continued)21
Table 2. Normal Pin Description (Continued)22
Port Structures24
Figure 9. General Purpose I/O Port24
Figure 10. External Interrupt I/O Port25
Memory Organization26
Program Memory26
Data Memory27
Figure 11. Program Memory Map27
Figure 12. Data Memory Map28
Figure 13. Lower 128Bytes of RAM28
External Data Memory29
Figure 14. XDATA Memory Area29
SFR Map30
SFR Map Summary30
Table 3. SFR Map Summary30
Table 4. XSFR Map Summary31
SFR Map32
Table 5. SFR Map32
Table 5. SFR Map (Continued)33
Table 5. SFR Map (Continued)34
Table 5. SFR Map (Continued)35
Table 6. XSFR Map36
Compiler Compatible SFR37
5 I/O Ports39
Port Register39
Data Register (Px)39
Direction Register (Pxio)39
Pull-Up Register Selection Register (Pxpu)39
Open-Drain Selection Register (Pxod)39
Bounce Enable Register (Pxdb)39
Port Function Selection Register (Pxfsr)39
Register Map40
Table 7. Port Register Map40
P0 Port41
P0 Port Description41
Register Description for P041
P1 Port44
P1 Port Description44
Register Description for P144
P2 Port48
P2 Port Description48
Register Description for P248
P3 Port50
P3 Port Description50
Register Description for P350
Interrupt Controller52
Figure 15. Interrupt Group Priority Level53
External Interrupt54
Figure 16. External Interrupt Description54
Block Diagram55
Figure 17. Interrupt Controller Block Diagram55
Interrupt Vector Table56
Table 8. Interrupt Vector Address Table56
Interrupt Sequence57
Figure 18. Interrupt Sequence Flow58
Effective Timing after Controlling Interrupt Bit59
Figure 19. Case A: Effective Timing of Interrupt Enable Register59
Figure 20. Case B: Effective Timing of Interrupt Flag Register59
Multi-Interrupt60
Figure 21. Effective Timing of Multi-Interrupt60
Interrupt Enable Accept Timing61
Interrupt Service Routine Address61
Saving/Restore General Purpose Registers61
Figure 22. Interrupt Response Timing Diagram61
Figure 23. Correspondence between Vector Table Address and the Entry Address of ISR61
Figure 24. Saving/Restore Process Diagram and Sample Source61
Interrupt Timing62
Figure 25. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction62
Interrupt Register Overview63
Interrupt Enable Register (IE, IE1, IE2, and IE3)63
Interrupt Priority Register (IP and IP1)63
External Interrupt Flag Register (EIFLAG0 and EIFLAG1)63
External Interrupt Polarity Register (EIPOL0L, EIPOL0H, EIPOL1 and EIPOL2)63
Register Map64
Table 9. Interrupt Register Map64
Interrupt Register Description65
Clock Generator70
Clock Generator Block Diagram71
Register Map71
Figure 26. Clock Generator Block Diagram71
Table 10. Clock Generator Register Map71
Register Description72
Basic Interval Timer74
BIT Block Diagram74
BIT Register Map74
Figure 27. Basic Interval Timer Block Diagram74
Table 11. Basic Interval Timer Register Map74
BIT Register Description75
Watchdog Timer76
Setting Window Open Period of Watchdog Timer77
Figure 28. Watch Dog Timer Interrupt Timing Waveform77
WDT Block Diagram78
Register Map78
Figure 29. Watch Dog Timer Block Diagram78
Table 12. Setting of Window Open Period78
Table 13. Watchdog Timer Register Map78
Register Description79
10 Watch Timer81
WT Block Diagram81
Figure 30. Watch Timer Block Diagram81
Register Map82
Watch Timer Register Description82
Table 14. Watch Timer Register Map82
Timer 0/1/284
Timer 084
8-Bit Timer/Counter Mode84
Table 15. Timer 0 Operating Mode84
Figure 31. 8-Bit Timer/Counter Mode for Timer 085
Figure 32. 8-Bit Timer/Counter 0 Example85
8-Bit PWM Mode86
Figure 33. 8-Bit PWM Mode for Timer 086
Figure 34. PWM Output Waveforms in PWM Mode for Timer 087
8-Bit Capture Mode88
Figure 35. 8-Bit Capture Mode for Timer 088
Figure 36. Input Capture Mode Operation for Timer 089
Figure 37. Express Timer Overflow in Capture Mode89
Timer 0 Block Diagram90
Register Map90
Figure 38. 8-Bit Timer 0 Block Diagram90
Table 16. Timer 0 Register Map90
Register Description91
Timer 192
Table 17. TIMER 1 Operating Modes92
16-Bit Timer/Counter Mode93
Figure 39. 16-Bit Timer/Counter Mode of Timer 193
Figure 40. 16-Bit Timer/Counter Mode Operation Example94
16-Bit Capture Mode95
Figure 41. 16-Bit Capture Mode of Timer 195
Figure 42. 16-Bit Capture Mode Operation Example96
Figure 43. Express Timer Overflow 16-Bit Capture Mode96
16-Bit PPG Mode97
Figure 44. 16-Bit PPG Mode of Timer 197
Figure 45. 16-Bit PPG Mode Operation Example98
16-Bit Complementary PWM Mode (Dead Time)99
Figure 46. 16-Bit Complementary PWM Mode for Timer 199
Figure 47. 16-Bit Complementary PWM Mode Timing Chart for Timer 1100
16-Bit Timer 1 Block Diagram101
Figure 48. 16-Bit Timer 1 Block Diagram101
Register Map102
Register Description102
Table 18. TIMER 1 Register Map102
Timer 2105
Table 19. TIMER 2 Operating Modes105
16-Bit Timer/Counter Mode106
Figure 49. 16-Bit Timer/Counter Mode of Timer 2106
Figure 50. 16-Bit Timer/Counter Mode Operation Example107
16-Bit Capture Mode108
Figure 51. 16-Bit Capture Mode of Timer 2108
Figure 52. 16-Bit Capture Mode Operation Example109
Figure 53. Express Timer Overflow in Capture Mode109
16-Bit PPG Mode110
Figure 54. 16-Bit PPG Mode of Timer 2110
Figure 55. 16-Bit PPG Mode Operation Example111
16-Bit Timer 2 Block Diagram112
Register Map112
Figure 56. 16-Bit Timer 2 Block Diagram112
Table 20. TIMER 2 Register Map112
Register Description113
12 Buzzer Driver115
Buzzer Driver Block Diagram115
Figure 57. Buzzer Driver Block Diagram115
Table 21. Buzzer Frequency at 8Mhz115
Register Map116
Register Description116
Table 22. Buzzer Driver Register Map116
13 12-Bit ADC117
Conversion Timing117
Block Diagram118
Figure 58. 12-Bit ADC Block Diagram118
Figure 59. A/D Analog Input Pin with a Capacitor118
ADC Operation119
Figure 60. Control Registers and Align Bits119
Figure 61. ADC Operation Flow Sequence119
Register Map120
Register Description120
Table 23. ADC Register Map120
14 I2C123
Block Diagram123
Figure 62. I 2 C Block Diagram123
Bit Transfer124
Start/ Repeated Start/ Stop124
Figure 63. Bit Transfer on the I2C-Bus124
Figure 64. START and STOP Condition124
Data Transfer125
Acknowledge125
Figure 65. Data Transfer on the I2C-Bus125
Synchronization/ Arbitration126
Figure 66. Acknowledge on the I2C-Bus126
Figure 67. Clock Synchronization During Arbitration Procedure126
Block Operation127
Figure 68. Arbitration Procedure of Two Masters127
I2C Block Initialization Process128
Figure 69. I2C SCL Max Clock, SCL, SDA Settings128
I2C Interrupt Service129
Master Transmitter130
Slave Receiver132
Register Map133
Table 24. I 2 C Register Map133
I2C Register Description134
Usart 0/1138
Block Diagram139
Figure 70. Usartn Block Diagram (N=0, 1)139
Clock Generation140
Figure 71. Clock Generation Block Diagram140
Table 25. Equations for Calculating Baud Rate Register Setting140
External Clock (XCK)141
Synchronous Mode Operation141
Figure 72. Synchronous Mode Xckn Timing (N = 0, 1)141
Data Format142
Figure 73. a Frame Format142
Parity Bit143
USART Transmitter143
Sending Tx Data143
Transmitter Flag and Interrupt144
Parity Generator144
Disabling Transmitter144
USART Receiver144
Receiving Rx Data145
Receiver Flag and Interrupt145
Parity Checker146
Disabling Receiver146
Asynchronous Data Reception146
Figure 74. Start Bit Sampling146
Figure 75. Sampling of Data and Parity Bit147
Figure 76. Stop Bit Sampling and Next Start Bit Sampling147
SPI Mode148
SPI Clock Formats and Timing148
Table 26. CPOL Functionality148
Figure 77. SPI Clock Formats When UCPHA = 0149
Figure 78. SPI Clock Formats When UCPHA = 1150
Receiver Time out (RTO)151
Figure 79. Example for RTO in USART151
Table 27. Example Condition of RTO151
Register Map152
Table 28. USART Register Map152
Register Description153
Baud Rate Settings (Example)160
Table 29. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies160
0% Error Baud Rate161
Figure 80. 0% Error Baud Rate Block Diagram161
16 Crc162
Block Diagram162
Figure 81. CRC Block Diagram162
Table 30. CRC Mode162
Register Map163
Table 31. CRC Register Map163
Register Description164
Polynomial166
17 Power down Operation167
Peripheral Operation in IDLE/ STOP Mode167
Table 32. Peripheral Operation Status During Power-Down Mode167
IDLE Mode168
Figure 82. IDLE Mode Release Timing by an External Interrupt168
STOP Mode169
Figure 83. STOP Mode Release Timing by External Interrupt169
Released Operation of STOP Mode170
Figure 84. STOP Mode Release Flow170
Register Map171
Register Description171
Table 33. Power-Down Operation Register Map171
18 Reset172
Reset Block Diagram172
Figure 85. Reset Block Diagram172
Table 34. Hardware Setting Values in Reset State172
Power on Reset173
Figure 86. Fast VDD Rising Time173
Figure 87. Internal RESET Release Timing on Power-Up173
Figure 88. Configuration Timing When Power-On174
Figure 89. Boot Process Waveform174
Table 35. Boot Process Description175
External Resetb Input176
Figure 90. Timing Diagram after RESET176
Figure 91. Oscillator Generating Waveform Example176
Low Voltage Reset Process177
Figure 92. Block Diagram of LVR177
Figure 93. Internal Reset at Power Fail Situation177
LVI Block Diagram178
Figure 94. Configuration Timing When LVR RESET178
Figure 95. LVI Block Diagram178
Register Map179
Reset Operation Register Description179
Table 36. Reset Operation Register Map179
19 Memory Programming182
Flash Control and Status Registers182
Register Map182
Table 37. Flash Control and Status Register Map182
Register Description183
Figure 96. Read Device Internal Checksum (Full Size)186
Figure 97. Read Device Internal Checksum (User Define Size)187
Table 38. Program and Erase Time188
Memory Map189
Flash Memory Map189
Figure 98. Flash Memory Map189
Figure 99. Address Configuration of Flash Memory189
Serial In-System Program Mode190
Flash Operation190
Figure 100. the Sequence of Page Program and Erase of Flash Memory190
Figure 101. the Sequence of Bulk Erase of Flash Memory191
Mode Entrance Method of ISP Mode195
Mode Entrance Method for ISP195
Figure 102. ISP Mode195
Table 39. Operation Mode195
Table 40. Mode Entrance Method for ISP195
Security196
Table 41. Security Policy Using Lock Bits196
Configure Option197
Password Function199
Table 42. Security Mode Using Password Lock Bit199
Figure 103. Using OCD/E-PGM+/E-GANG4/E-GANG6200
20 Electrical Characteristics201
Absolute Maximum Ratings201
Recommended Operating Conditions201
Table 43. Absolute Maximum Ratings201
Table 44. Recommended Operating Conditions201
A/D Converter Characteristics202
Table 45. A/D Converter Characteristics202
VDC1.55 Reference Voltage Characteristics203
Power on Reset Characteristics203
Table 47. VDC1.55 Reference Voltage Characteristics203
Table 48. Power-On Reset Characteristics203
Low Voltage Reset and Low Voltage Indicator Characteristics204
Table 49. LVR and LVI Characteristics204
High Speed Internal RC Oscillator Characteristics205
Low Speed Internal RC Oscillator Characteristics205
Table 50. High Speed Internal RC Oscillator Characteristics205
Table 51. Low Speed Internal RC Oscillator Characteristics205
DC Characteristics206
Table 52. DC Characteristics206
AC Characteristics207
Figure 104. AC Timing207
Table 53. AC Characteristics207
USART Characteristics208
Table 54. USART Timing Characteristics in SYNC. or SPI Mode Operations208
Figure 105. SPI Master Mode Timing (UCPHA = 0, MSB First)209
Figure 106. Spi/Synchronous Master Mode Timing (UCPHA = 1, MSB First)209
Figure 107. SPI Slave Mode Timing (UCPHA = 0, MSB First)210
Figure 108. Spi/Synchronous Slave Mode Timing (UCPHA = 1, MSB First)210
SPI Characteristics211
Figure 109. SPI0/1 Timing211
Table 55. SPI Characteristics211
I2C Characteristics212
Figure 110. I2C Timing212
Table 56. I2C Characteristics212
Data Retention Voltage in Stop Mode213
Figure 111. Stop Mode Release Timing When Initiated by an Interrupt213
Figure 112. Stop Mode Release Timing When Initiated by RESETB213
Table 57. Data Retention Voltage in Stop Mode213
Internal Flash ROM Characteristics214
Input/Output Capacitance214
Table 58. Internal Flash Rom Characteristics214
Table 59. Input / Output Capacitance214
Main Clock Oscillator Characteristics215
Figure 113. Crystal/Ceramic Oscillator215
Figure 114. External Clock215
Table 60. Main Clock Oscillator Characteristics215
Sub-Clock Oscillator Characteristics216
Figure 115. Crystal Oscillator216
Figure 116. Crystal Oscillator216
Table 61. Sub Clock Oscillator Characteristics216
Main Oscillation Stabilization Characteristics217
Sub-Oscillation Characteristics217
Figure 117. Clock Timing Measurement at XIN217
Figure 118. Clock Timing Measurement at SXIN217
Table 62. Main Oscillation Stabilization Characteristics217
Table 63. Sub Oscillation Stabilization Characteristics217
Operating Voltage Range218
Recommended Circuit and Layout218
Figure 119. Operating Voltage Range218
Figure 120. Recommended Voltage Range218
Typical Characteristics219
Figure 121. RUN (IDD1) Current219
Figure 122. IDLE (IDD2) Current220
Figure 123. SUB RUN (IDD3) Current220
Figure 124. SUB IDLE (IDD4) Current221
Figure 125. SUB IDLE (IDD4) Current221
21 Package Information222
16 SOPN Package Information222
Figure 126 16 SOPN Package Outline222
20 TSSOP Package Information223
Figure 127. 20 TSSOP Package Outline223
20 SOP Package Information224
Figure 128. 20 SOP Package Outline224
24 QFN Package Information225
Figure 129. 24 QFN Package Outline225
28 SOP Package Information226
Figure 130. 28 SOP Package Outline226
32 LQFP Package Information227
Figure 131. 32 LQFP Package Outline227
22 Development Tools228
Compiler228
OCD (On-Chip Debugger) Emulator and Debugger228
Figure 132. Debugger (OCD1/OCD2) and Pinouts228
Programmers229
OCD Emulator229
Gang Programmer229
Figure 133. E-PGM+ (Single Writer) and Pinouts229
Flash Programming230
On-Board Programming230
Figure 134. E-Gang4 and E-Gang6 (for Mass Production)230
Table 64. Pins for Flash Programming230
Circuit Design Guide231
Figure 135. PCB Design Guide for On-Board Programming231
On-Chip Debug System232
Figure 136. On-Chip Debugging System in Block Diagram232
Table 65. OCD Features232
Two-Pin External Interface233
Figure 137. 10-Bit Transmission Packet233
Figure 138. Data Transfer on Twin Bus234
Figure 139. Bit Transfer on Serial Bus234
Figure 140. Start and Stop Condition234
Figure 141. Acknowledge on Serial Bus235
Figure 142. Clock Synchronization During Wait Procedure235
Figure 143. Connection of Transmission236
23 Ordering Information237
Table 66. A96G166/A96A166/A96S166 Device Ordering Information237
Figure 144. A96G166/A96A166/A96S166 Device Numbering Nomenclature238
Appendix239
Instruction Table239
Table 67. Instruction Table239
Revision History245

Abov A96G166 - Figure 77. SPI Clock Formats When UCPHA = 0

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