Figure 78. SPI Clock Formats when UCPHA = 1
When UCPHA=1, the slave begins to drive its MISOn output when SSn goes active low, but the data
is not defined until the first XCKn edge. The first XCKn edge shifts the first bit of data from the shifter
onto the MOSIn output of the master and the MISOn output of the slave.
The next XCKn edge causes both the master and slave to sample the data bit value on their MISOn
and MOSIn inputs, respectively.
At the third XCKn edge, the USARTn shifts the second data bit value out to the MOSIn and MISOn
output of the master and slave respectively. When UCPHA=1, the slave’s SSn input is not required to
go to its inactive high level between transfers.
Because the SPI logic reuses the USARTn resources, SPI mode of operation is similar to that of
synchronous or asynchronous operation. An SPI transfer is initiated by checking for the USARTn
Data Register Empty flag (UDRE=1) and then writing a byte of data to the UDATA Register. In master
mode of operation, even if transmission is not enabled (TXE=0), writing data to the UDATA register is
necessary because the clock XCKn is generated from transmitter block.
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