11.3 Timer 2
A 16-bit timer 2 consists of a multiplexer, timer 2 A data high/low register, timer 2 B data high/low
register and timer 2 control high/low register (T2ADRH, T2ADRL, T2BDRH, T2BDRL, T2CRH, and
T2CRL).
Timer 2 operates in one of the following modes:
ï‚Ÿ 16-bit timer/counter mode
ï‚Ÿ 16-bit capture mode
ï‚Ÿ 16-bit PPG output mode (one-shot mode)
ï‚Ÿ 16-bit PPG output mode (repeat mode)
The timer/counter 2 can be a divided clock of a system clock which is selected from prescaler output,
external clock(EC2) and T1 A Match (timer 1 A match signal). The clock source is selected by a clock
selection logic, controlled by clock selection bits (T2CK[2:0]).
ï‚Ÿ TIMER 2 clock source: f
X
/1, f
X
/2, f
X
/4, f
X
/8, f
X
/128, f
X
/512, EC2 and T1 A Match
In capture mode, data is captured into input capture data registers (T2BDRH/T2BDRL) by EINT12. In
timer/counter mode, whenever counter value is equal to T2ADRH/L, T2O port toggles. In addition, the
timer 2 outputs PWM waveform to PWM2O port in the PPG mode.
Table 19. TIMER 2 Operating Modes
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