Figure 66. Acknowledge on the I2C-Bus
14.6 Synchronization/ arbitration
Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line.
This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start
counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state is
reached. However the LOW to HIGH transition of this clock may not change the state of the SCL line
if another clock is still within its LOW period. In this way, a synchronized SCL clock is generated with
its LOW period determined by the device with the longest clock LOW period, and its HIGH period
determined by the one with the shortest clock HIGH period.
A master may start a transfer only if the bus is free. Two or more masters may generate a START
condition. Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a
way that the master which transmits a HIGH level, while another master is transmitting a LOW level
will switch off its DATA output state because the level on the bus doesn’t correspond to its own level.
Arbitration continues for many bits until a winning master gets the ownership of I
2
C bus. Its first stage
is comparison of the address bits.
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