Abov A96G166 - USART Characteristics; Table 54. USART Timing Characteristics in SYNC. or SPI Mode Operations

20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual
208
20.11 USART characteristics
The following table and figures show USART timing condition in SPI or Synchronous mode operation.
Table 54. USART Timing Characteristics in SYNC. or SPI Mode Operations
(T
A
= -40°C ~ +85°C or T
A
=-40°C ~ 105°C, VDD=1.8V ~ 5.5V)
Parameter
Symbol
MIN
MAX
Unit
System clock period(0.5MHz~16MHz)
t
SCLK
62.5
2000
ns
Clock (XCK) period
t
XCK
4 x t
SCLK
1028 x t
SCLK
ns
Clock (XCK) high time
t
XCKH
2 x t
SCLK
514 x t
SCLK
ns
Clock (XCK) low time
t
XCKL
2 x t
SCLK
514 x t
SCLK
ns
Lead time
Master
Slave
t
LEAD
t
LEAD
0.5 x t
XCK
2 x t
SCLK
0.5 x t
XCK
–
ns
Lag time
Master
Slave
t
LAG
t
LAG
0.5 x t
XCK
2 x t
SCLK
0.5 x t
XCK
–
ns
Data setup time (inputs)
Master
Slave
t
SIM
t
SIS
2 x t
SCLK
2 x t
SCLK
2 x t
SCLK
2 x t
SCLK
ns
Data hold time (inputs)
Master
Slave
t
HIM
t
HIS
10
10
–
–
ns
Data setup time (outputs)
Master
Slave
t
SOM
t
SOS
2 x t
SCLK
2 x t
SCLK
2 x t
SCLK
2 x t
SCLK
ns
Data hold time (outputs)
Master
Slave
t
HOM
t
HOS
-10
-10
–
–
ns
Disable time
t
DIS
1 x t
SCLK
2 x t
SCLK
ns
NOTE:
1. In synchronous mode, Lead and Lag time for SS pin is ignored. And the case of “UCPHA=0”
is also only applied to SPI mode
2. All timing is shown between 20% VDD and 80% VDD.