Abov A96G166 User Manual

A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2
93
11.2.1 16-bit timer/counter mode
16-bit timer/counter mode is selected by control registers, and the 16-bit timer/counter has counter
registers and data registers as shown in Figure 39. The counter register is increased by internal or
external clock input. Timer 1 can use the input clock with one of 1, 2, 4, 8, 64, 2048 and High-speed
internal RC oscillator (HSI) prescaler division rates (T1CK[2:0]). When the value of T1CNTH, T1CNTL
and the value of T1ADRH, T1ADRL are identical to each other in Timer 1, a match signal is generated
and the interrupt of Timer1 occurs. The T1CNTH, T1CNTL value is automatically cleared by the
match signal. It can be cleared by software (T1CC) too.
The external clock (EC1) counts up the timer at the rising edge. If the EC1 is selected as a clock
source by T1CK[2:0], EC1 port should be set to the input port by P12IO bit.
T1EN
T1CRH
1
ADDRESS:BBH
INITIAL VALUE : 0000_0000B
T1MS[1:0]
T1POL
A Match
T1CC
T1EN
P
r
e
s
c
a
l
e
r
fx
M
U
X
fx/2
fx/4
fx/64
fx/2048
fx/8
fx/1
16-bit Counter
T1CNTH/T1CNTL
Clear
Edge
Detector
T1ECE
EC1
Comparator
16-bit A Data Register
T1ADRH/T1ADRL
T1IFR
INT_ACK
Clear
To interrupt
block
A Match
Buffer Register A
A Match
T1CC
Reload
Pulse
Generator
T1O
R
T1EN
3
T1CK[2:0]
2
T1BEN T1MS1 T1MS0
– –
T1PE T1CC
X 0 0
– –
X X
T1CK2
T1CRL
X
ADDRESS:BAH
INITIAL VALUE : 0000_0000B
T1CK1 T1CK0 T1IFR T1BPOL T1POL T1ECE T1CNTR
X X X X X X X
T1EN
T1PE
HSIRC
Figure 39. 16-bit Timer/Counter Mode of Timer 1

Abov A96G166 Specifications

General

Brand	Abov
Model	A96G166
Category	Computer Hardware
Language	English