14.7.4 Slave receiver
When both the IIC and the INTEN of the I2CMR are enabled, the I2C block monitors I2C bus lines for
the start condition and the self-address with I2CSAD. To have both signals of start signal and getting
self-address, the I2C block generates I2C interrupts with the status bits (SSEL, BUSY RXACK,
SLAVE mode, and so on) after sending an ACK signal. At the time, the I2C block controls SCL line to
low state to be ready to get/handle the next I2C data.
By the I2C interrupt service if the I2C block is ready for the next step, it is to release the SCL line to
high state to get the next SCL clock from the master. The I2C block decides the bus direction (data
receive/transmission) by using a data direction (R/Wî¡) bit in Slave address from master. The state of
bus direction is set in the TMOD bit of the I2CSR register.
If the master generates Stop condition, the I2C block receives STOP condition and generates the I2C
interrupt. The I2C interrupt service writes any data to I2CSR and finishes the Slave operation.
Example code for the slave mode is introduced below:
I2C Interrupt service
I2C Slave service
if(Getting SSEL and send ACK) // received Self-address form master
if(TMODE) // data direction (R/W)
I2CDR=I2C_TXData // Transmission mode, Load data
else
I2C_RXData =I2CDR
else
if (Get STOP condition)
else
if (TMODE) // data direction (R/W)
I2CDR= I2C_TXData // Transmission mode, Load data
else
I2C_RXData =I2CDR // Save received Data
I2CSR=0xff;
To Next Page
Loading...
Need help?
General
