Abov A96G166 - Register Description

A96G166/A96A166/A96S166 User’s manual 9. Watchdog timer
79
9.4 Register description
WDTCNTH (Watch Dog Timer Counter High Register): 1012H
7
6
5
4
3
2
1
0
WDTCNTH 7
WDTCNTH 6
WDTCNTH 5
WDTCNTH 4
WDTCNTH 3
WDTCNTH 2
WDTCNTH 1
WDTCNTH 0
R
R
R
R
R
R
R
R
Initial value: 00H
WDTCNTH[7:0]
WDT Counter High
WDTCNTL (Watch Dog Timer Counter Low Register): 1013H
7
6
5
4
3
2
1
0
WDTCNTL 7
WDTCNTL 6
WDTCNTL 5
WDTCNTL 4
WDTCNTL
WDTCNTL 2
WDTCNTL 1
WDTCNTL 0
R
R
R
R
R
R
R
R
Initial value: 00H
WDTCNTL[7:0]
WDT Counter Low
WDTC (Watch Dog Timer Clear Register): 1010H
7
6
5
4
3
2
1
0
WDTC7
WDTC6
WDTC5
WDTC4
WDTC3
WDTC2
WDTC1
WDTC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
WDTC[7:0]
WDT Counter Clear
Others
Reset occurs
10010110
WDT counter clear and start again
WDTSR (Watch Dog Timer Status Register): 1011H
7
6
5
4
3
2
1
0
–
–
–
–
–
–
WSTATE
WDTIFR
–
–
–
–
–
–
R
R/W
Initial value: 00H
WSTATE
Window Status
0
Close window
1
Open window
WDTIFR
When WDT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write
‘0’ to this bit or auto clear by INT_ACK signal.
0
WDT Interrupt no generation.
1
WDT Interrupt generation.
WDTIDR (Watch Dog Timer Identification Register): 8EH
7
6
5
4
3
2
1
0
WDTIDR 7
WDTIDR 6
WDTIDR 5
WDTIDR 4
WDTIDR 3
WDTIDR 2
WDTIDR 1
WDTIDR 0
W
W
W
W
W
W
W
W
Initial value: 00H
WDTIDR[7:0]
WDT Identification for a WDTCR
Others
No identification value.
01011001
Identification value for a WDTCR write.
NOTE: These bits are automatically cleared to logic ‘00H’
immediately after WDTCR write.