Abov A96G166 - Interrupt Register Overview; Interrupt Enable Register (IE, IE1, IE2, and IE3); Interrupt Priority Register (IP and IP1); External Interrupt Flag Register (EIFLAG0 and EIFLAG1)

A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller
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6.11 Interrupt register overview
6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3)
Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control
bits. Total 21 peripherals are able to control interrupt.
6.11.2 Interrupt Priority Register (IP and IP1)
21 interrupts are divided into 2 groups which have 4 interrupt sources respectively. A group can be
assigned to 4 levels of interrupt priority using interrupt priority register. Level 3 is the highest priority,
while level 0 is the lowest priority.
After a reset, IP and IP1 are cleared to ‘00H’. If interrupts have the same priority level, lower number
interrupt is served first.
6.11.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1)
External Interrupt Flag 0 Register (EIFLAG0) and External Interrupt Flag 1 Register (EIFLAG1) are
set to ‘1’ when the external interrupt generating condition is satisfied. These flags are cleared when
the interrupt service routine is executed. Alternatively, these flags can be cleared by writing ‘0’ on to
themselves.
6.11.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, EIPOL1 and EIPOL2)
External Interrupt Polarity0 high/low Register (EIPOL0H/L), External Interrupt Polarity1 Register
(EIPOL1) and External Interrupt Polarity2 Register (EIPOL2) determines an edge type from rising
edge, falling edge, and both edges of interrupt. Initially, default value is no interrupt at any edge.