Abov A96G166 - Effective Timing after Controlling Interrupt Bit; Figure 19. Case A: Effective Timing of Interrupt Enable Register; Figure 20. Case B: Effective Timing of Interrupt Flag Register

A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller
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6.5 Effective timing after controlling interrupt bit
Case A in Figure 19 shows the effective time after controlling the Interrupt Enable Registers (IE, IE1,
IE2, and IE3).
Figure 19. Case A: Effective Timing of Interrupt Enable Register
Case B in Figure 20 shows the effective time after controlling Interrupt Flag Registers.
Figure 20. Case B: Effective Timing of Interrupt Flag Register
Interrupt Enable Register
command
Next Instruction
Next Instruction
After executing IE set/clear,
enable register is effective.
Interrupt Flag Register
Command
Next Instruction
Next Instruction
After executing next instruction,
interrupt flag result is effective.