Figure 68. Arbitration Procedure of Two Masters
14.7 Block operation
The I2C block as peripheral design is independently operating with main CPU operation. The
operation of I2C block does a byte unit of I2C frame. After finishing a byte operation (transmit/receive
data and clock) on I2C bus system, I2C block generate I2C interrupt for next byte operation. The I2C
Interrupt service manage I2C block with the SFR registers, data load/read register (I2CDR) from/to
I2C bus system, block control register (I2CMR), the state register (I2CSR) contained operation result.
An operation unit of I2C H/W block generates/ receive 9 SCL clock that are for 8 bits data and an
ACK. I2C block send / receive ACK signal at 9th clock of SCL according to I2C specification.
The I2C application software initialize I2C block condition depended on clock system, I2C devices
condition after system power on.
An application S/W prepares I2C bus communication resource on RAM buffers. If it is to set the start
flag in I2CMR register. I2C block start to generate start signal and send a Slave address to slave
device. All steps of I2C communication service except start signal and slave address is done by H/W
block and I2C Interrupt service. Therefore main application software can reduce time resource while
I2C Data write/read operation.
I2C block design supports both functions of master/ Slave on the same block. In case of Masker
device it generate SCL clock to slave device and the case of slave mode receive SCL clock from
master device.
I2C block decide SDA data direction with the data direction bit (R/Wî¡) of device address in both cases
of master and slave mode (TMODE bit 0-> Receive, 1-> Transmit).
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