Abov A96G166 - 6.2 Block diagram

A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller
55
6.2 Block diagram
0
0
0
0
Priority High
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
17
17
17
17
18
18
18
18
19
19
19
19
20
20
20
20
21
21
21
21
22
22
22
22
23
23
23
23 Priority Low
EA
Release
Stop/Sleep
EINT10
EIFLAG1.4
EIFLAG1.5
EINT11
EINT1
EIFLAG0.0
EINT3
EINT0
EINT2
EINT4
EIFLAG0.1
EIFLAG0.2
EIFLAG0.3
EIFLAG0.4
Usart0 Tx
Timer 0
Timer 1
Timer 2
IP1IP
IE
FLAG10
FLAG11
IE2
T0OVIFR
T0IFR
T1IFR
T2IFR
EIPOL1
I2C
Usart1 Rx
Usart1 Tx
IE1
I2CIFR
ADC
WT
WDT
BIT
ADCIFR
WTIFR
WDTIFR
BITIFR
Level 0
Level 1
Level 2
Level 3
EIPOL0H/L
CRC
CRC_FL
AG
IE3
EINT5
EIFLAG0.5
FLAG5
EIPOL0H
EIFLAG1.6
EINT12
FLAG12
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
EINT6
EIFLAG0.6
FLAG6
EINT8
EIFLAG1.0
EINTA
EINT7
EINT9
EIFLAG1.1
EIFLAG1.2
EIFLAG1.3
EIPOL2
FLAG7
FLAG8
FLAG9
FLAGA
Usart0 Rx
LVIFR
LVI
NOTES:
1. The release signal for stop/idle mode may be generated by all interrupt sources which are enabled
without reference to the priority level.
2. An interrupt request is delayed while data are written to IE, IE1, IE2, IE3, IP, IP1, and PCON
register.
Figure 17. Interrupt Controller Block Diagram