17.3 STOP mode
Power control register is set to ‘03H’ to enter into STOP mode. In STOP mode, the selected oscillator,
system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub
clock.
With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.
For example, If the internal RC oscillator (f
IRC
) is selected for the system clock and the sub clock (f
SUB
)
is oscillated, the internal RC oscillator stops oscillation and the sub clock is continuously oscillated in
stop mode. At that time, the watch timer can be operated with the sub clock.
Sources to exit from STOP mode is hardware reset and interrupts. The hardware reset re-defines all
control registers. When awaking from STOP mode, enough oscillation stabilization time is required to
normal operation. Figure 83 shows the timing diagram.
As shown in the Figure 83, when released from STOP mode, the basic interval timer is activated on
wake-up. Therefore, before STOP instruction, a user must set relevant prescale divide ratio to have
long enough time. This guarantees that an oscillator has started and stabilized.
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