15.2 Clock generation
The Clock generation logic generates a base clock signal for the transmitter and the receiver. The
USART supports four modes of clock operation such as Normal Asynchronous mode, Double Speed
Asynchronous mode, Master Synchronous mode, and Slave Synchronous mode.
Clock generation scheme for Master SPI and Slave SPI mode is the same as Master Synchronous
and Slave Synchronous operation mode. The UMSEL[1:0] bit in UnCTRL1 register selects between
asynchronous and synchronous operation. Asynchronous Double Speed mode is controlled by the
U2X bit in the UnCTRL2 register. The MASTER bit in UnCTRL2 register controls whether the clock
source is internal (Master mode, output port) or external (Slave mode, input port). The XCKn pin is
only active when the USART operates in Synchronous or SPI mode.
Figure 71. Clock Generation Block Diagram
Table 25 contains equations for calculating the baud rate (in bps).
Table 25. Equations for Calculating Baud Rate Register Setting
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