11.2 Timer 1
A 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register
high/low and timer 1 control register high/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH,
T1CRL).
Timer 1 operates in one of the following modes:
ï‚Ÿ 16-bit timer/counter mode
ï‚Ÿ 16-bit capture mode
ï‚Ÿ 16-bit PPG output mode (one-shot mode)
ï‚Ÿ 16-bit PPG output mode (repeat mode)
The timer/counter 1 uses an internal clock or an external clock (EC1) as an input clock source. The
clock sources are introduced below, and one is selected by clock selection logic which is controlled by
clock selection bits (T1CK[2:0]).
ï‚Ÿ TIMER 1 clock source: f
X
/1, f
X
/2, f
X
/4, f
X
/8, f
X
/64, f
X
/2048, HSI and EC1
In capture mode, the data is captured into input capture data register (T1BDRH/T1BDRL) by EINT11.
Timer 1 results in the comparison between counter and data register through T1O port in
timer/counter mode. In addition, Timer 1 outputs PWM waveform through PWM1O port in the PPG
mode.
Table 17. TIMER 1 Operating Modes
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