15 USART 0/1
Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly
flexible serial communication device. A96G166/A96A166/A96S166 has two USART function blocks,
USART0 and USART1 are absolutely same functionally.
Main features of the USART0/1 are listed below:
 Full Duplex Operation (Independent Serial Receive and Transmit Registers)
 Asynchronous or Synchronous Operation
 Master or Slave Clocked Synchronous and SPI Operation
 Supports all four SPI Modes of Operation (Mode 0, 1, 2, 3)
 LSB First or MSB First Data Transfer @SPI mode
 High Resolution Baud Rate Generator
 Supports Serial Frames with 5,6,7,8, or 9 Data bits and 1 or 2 Stop bits
 Odd or Even Parity Generation and Parity Check Supported by Hardware
 Data OverRun Detection
 Framing Error Detection
 Digital Low Pass Filter
 Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
 Double Speed Asynchronous Communication Mode
The USART has three main parts such as a Clock generator, Transmitter and Receiver.
The Clock generation logic consists of a synchronization logic for external clock input used by
synchronous or SPI slave operation, and a baud rate generator for asynchronous or master
(synchronous or SPI) operation.
The Transmitter consists of a single write buffer, a serial shift register, parity generator and control
logic for handling different serial frame formats. Write buffer allows a continuous transfer of data
without any delay between frames.
The Receiver is the most complex part of the USART module due to its clock and data recovery units.
The recovery unit is used for asynchronous data reception. In addition to the recovery unit, the
receiver includes a parity checker, a shift register, a two level receive FIFO (UDATA) and a control
logic.