15.8.1 Receiving Rx data
When USART is in synchronous or asynchronous operation mode, the Receiver starts data reception
when it detects a valid start bit (LOW) on RXDn pin. Each bit after start bit is sampled at pre-defined
baud-rate (asynchronous) or sampling edge of XCKn (synchronous), and shifted into the receive shift
register until the first stop bit of a frame is received.
Even if there’s 2nd stop bit in the frame, the 2nd stop bit is ignored by the Receiver. That is, receiving
the first stop bit means that a complete serial frame is present in the receiver shift register and
contents of the shift register are to be moved into the receive buffer. The receive buffer is read by
reading the UDATA register.
If 9-bit characters are used (USIZE[2:0] = 7), the ninth bit is stored in the RX8 bit position in the
UnCTRL3 register. The 9th bit must be read from the RX8 bit before reading the low 8 bits from the
UDATA register. Likewise, the error flags FE, DOR, PE must be read before reading the data from
UDATA register. This is because the error flags are stored in the same FIFO position of the receive
buffer.
15.8.2 Receiver flag and interrupt
The USART Receiver has one flag that indicates the Receiver state. Receive Complete (RXC) flag
indicates whether there are unread data present in the receive buffer. This flag is set when there are
unread data in the receive buffer and cleared when the receive buffer is empty. If the Receiver is
disabled (RXE=0), the receiver buffer is flushed and the RXC flag is cleared.
When the Receive Complete Interrupt Enable (RXCIE) bit in the UnCTRL2 register is set and Global
Interrupt is enabled, the USART Receiver Complete Interrupt is generated while RXC flag is set.
The USART Receiver has three error flags which are Frame Error (FE), Data OverRun (DOR) and
Parity Error (PE). These error flags can be read from the USTAT register. As data received are stored
in the 2-level receive buffer, these error flags are also stored in the same position of receive buffer. So,
before reading received data from UDATA register, read the USTAT register first which contains error
flags.
The Frame Error (FE) flag indicates the state of the first stop bit. The FE flag is set when the stop bit
was correctly detected as “1”, and the FE flag is cleared when the stop bit was incorrect, i.e. detected
as “0”. This flag can be used for detecting out-of-sync conditions between data frames.
The Data OverRun (DOR) flag indicates data loss due to a receive buffer full condition. A DOR occurs
when the receive buffer is full, and another new data is present in the receive shift register which are
to be stored into the receive buffer. After the DOR flag is set, all the incoming data are lost. To
prevent data loss or clear this flag, read the receive buffer.
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