Abov A96G166 - Table of Contents

Contents A96G166/A96A166/A96S166 User’s manual
2
Contents
Introduction.............................................................................................................................................. 1
Reference document ............................................................................................................................... 1
1 Description ................................................................................................................................... 12
1.1 Device overview .................................................................................................................. 12
1.2 A96G166/A96A166/A96S166 block diagram ...................................................................... 14
2 Pinouts and pin description .......................................................................................................... 15
2.1 Pinouts ................................................................................................................................ 15
2.2 Pin description..................................................................................................................... 20
3 Port structures .............................................................................................................................. 24
4 Memory organization .................................................................................................................... 26
4.1 Program memory ................................................................................................................ 26
4.2 Data memory ....................................................................................................................... 27
4.3 External data memory ......................................................................................................... 29
4.4 SFR map ............................................................................................................................. 30
4.4.1 SFR map summary ................................................................................................ 30
4.4.2 SFR map ................................................................................................................ 32
4.4.3 Compiler compatible SFR ...................................................................................... 37
5 I/O ports ....................................................................................................................................... 39
5.1 Port register ......................................................................................................................... 39
5.1.1 Data register (Px) ................................................................................................... 39
5.1.2 Direction register (PxIO) ......................................................................................... 39
5.1.3 Pull-up register selection register (PxPU) .............................................................. 39
5.1.4 Open-drain Selection Register (PxOD) .................................................................. 39
5.1.5 De-bounce Enable Register (PxDB) ...................................................................... 39
5.1.6 Port Function Selection Register (PxFSR) ............................................................. 39
5.1.7 Register Map .......................................................................................................... 40
5.2 P0 port ................................................................................................................................. 41
5.2.1 P0 port description ................................................................................................. 41
5.2.2 Register description for P0 ..................................................................................... 41
5.3 P1 port ................................................................................................................................. 44
5.3.1 P1 port description ................................................................................................. 44
5.3.2 Register description for P1 ..................................................................................... 44
5.4 P2 port ................................................................................................................................. 48
5.4.1 P2 port description ................................................................................................. 48
5.4.2 Register description for P2 ..................................................................................... 48
5.5 P3 port ................................................................................................................................. 50
5.5.1 P3 port description ................................................................................................. 50
5.5.2 Register description for P3 ..................................................................................... 50
6 Interrupt controller ........................................................................................................................ 52
6.1 External interrupt ................................................................................................................. 54
6.2 Block diagram ..................................................................................................................... 55
6.3 Interrupt vector table ........................................................................................................... 56
6.4 Interrupt sequence .............................................................................................................. 57
6.5 Effective timing after controlling interrupt bit ....................................................................... 59
6.6 Multi-interrupt ...................................................................................................................... 60
6.7 Interrupt enable accept timing ............................................................................................. 61
6.8 Interrupt service routine address ........................................................................................ 61