Abov A96G166 - Page 121

A96G166/A96A166/A96S166 User’s manual 13. 12-bit ADC
121
ADCCRH (A/D Converter High Register): 9DH
7
6
5
4
3
2
1
0
ADCIFR
IREF
TRIG2
TRIG1
TRIG0
ALIGN
CKSEL1
CKSEL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 01H
ADCIFR
When ADC interrupt occurs, this bit becomes ‘1’. For clearing bit,
write ‘0’ to this bit or auto clear by INT_ACK signal. Writing “1” has
no effect.
0
ADC Interrupt no generation
1
ADC Interrupt generation
IREF
Select internal voltage reference.
0
External input signal source select
1
Test only
TRIG[2:0]
A/D Trigger Signal Selection
TRIG2
TRIG1
TRIG0
Description
0
0
0
ADST
0
0
1
Timer 0 A match signal
0
1
0
Timer 2 A match signal
0
1
1
EINT0~4
1
0
0
EINT5
1
0
1
EINT6
Other Values
Not used
ALIGN
A/D Converter data align selection.
0
MSB align (ADCDRH[7:0], ADCDRL[7:4])
1
LSB align (ADCRDH[3:0], ADCDRL[7:0])
CKSEL[1:0]
A/D Converter Clock selection
CKSEL1
CKSEL0
Description
0
0
fx/1
0
1
fx/2
1
0
fx/4
1
1
fx/8
NOTES:
1. fx : system clock
2. ADC clock should use below 8MHz