15. USART 0/1 A96G166/A96A166/A96S166 User’s manual
UCTRL2 (USART Control 2 Register) CCH/F2H
Interrupt enable bit for USART Data Register Empty.
Interrupt from UDRE is inhibited (use polling)
When UDRE is set, request an interrupt
Interrupt enable bit for Transmit Complete.
Interrupt from TXC is inhibited (use polling)
When TXC is set, request an interrupt
Interrupt enable bit for Receive Complete
Interrupt from RXC is inhibited (use polling)
When RXC is set, request an interrupt
Interrupt enable bit for Asynchronous Wake in STOP mode. When
device is in stop mode, if RXD2 goes to LOW level an interrupt can
be requested to wake-up system.
Interrupt from Wake is inhibited
When WAKE is set, request an interrupt
NOTE) WAKEIE must set after USARTEN setting ‘1’.
Enables the transmitter unit.
Enables the receiver unit.
Activate USART module by supplying clock.
USART is disabled (clock is halted)
This bit only has effect for the asynchronous operation and selects
receiver sampling rate.
Normal asynchronous operation
Double Speed asynchronous operation