ARM Cortex A9 User Manual

System Control
ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-44
ID073015 Non-Confidential
Table 4-51 shows the TLB VA Register bit assignments.
Figure 4-26 shows the bit arrangement of the memory space identifier.
Figure 4-26 Memory space identifier format
Figure 4-27 shows the TLB PA Register bit assignment.
Figure 4-27 TLB PA Register bit assignments
Table 4-52 describes the functions of the TLB PA Register bits.
Table 4-51 TLB VA Register bit assignments
Bits Name Function
[31:12] VPN Virtual page number.
Bits of the virtual page number that are not translated as part of the page table translation because the size of the
tables is
UNPREDICTABLE when read and SBZ when written.
[11] - UNK/SBZP.
[10] NS NS bit.
[9:0] Process Memory space identifier.
987 0
1 UNK/SBZP
0 ASID
Global entries
Address Space Identifier entries
UNK/SBZP
VPPN
31 11 8 6 5 4 3 1 0
AP
12
SZ
7
UNK/SBZP UNK/SBZP
Table 4-52 TLB PA Register bit assignments
Bits Name Function
[31:12] PPN Physical Page Number.
Bits of the physical page number that are not translated as part of the page table translation are
UNPREDICTABLE
when read and SBZP when written.
[11:8] - UNK/SBZP.
[7:6] SZ Region Size:
b00 16MB Supersection
b01 4KB page
b10 64KB page
b11 1MB section.
All other values are reserved.

ARM Cortex A9 Specifications

General

Architecture	ARMv7-A
Cores	1-4
SIMD Extensions	NEON
ISA	ARM
Microarchitecture	Cortex-A9
Instruction Width	32-bit
Data Width	32-bit
MMU	Yes
Instruction Set	ARMv7-A
Clock Speed	Up to 2 GHz
L1 Cache	32 KB Instruction, 32 KB Data (per core)
Process Technology	40 nm, 28 nm
Floating Point Unit	VFPv3
Pipeline Depth	8 stages
Power Consumption	Low power design