Fujitsu 8FX

MB95630H Series
90 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 7 TIME-BASE TIMER
7.2 Configuration
● Time-base timer counter
This is a 24-bit downcounter using the main clock divided by two, the main CR clock or the
main CR PLL clock as its count clock.
● Counter clear circuit
This circuit controls the clearing of the time-base timer counter.
● Interval timer selector
This circuit selects one bit out of 16 bits in the 24 bits of the time-base timer counter as the
interval timer.
● Time-base timer control register (TBTC)
This register selects the interval time, clears the counter, controls interrupts and checks the
state of the time-base timer.
■ Input Clock
The time-base timer uses the main clock divided by two, the main CR clock or the main CR
PLL clock as its input clock (count clock).
■ Output Clock
The time-base timer supplies clocks to the clock supervisor counter, the software watchdog
timer and the prescaler.