Fujitsu 8FX User Manual

MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 73
CHAPTER 5 INTERRUPTS
5.1 Interrupts
5.1.1 Interrupt Level Setting Registers (ILR0 to ILR5)
The interrupt level setting registers (ILR0 to ILR5) contain 24 pairs of 2-bit data
assigned to the interrupt requests of different peripheral functions. Each pair
of bits (interrupt level setting bits) is used to set the interrupt level of an
interrupt request.
■ Register Configuration
The interrupt level setting registers assign a pair of bits to every interrupt request. The values
of interrupt level setting bits in these registers represent the priority of an interrupt request
(interrupt level: 0 to 3) in interrupt processing.
ILR0
bit 7 6 5 4 3 2 1 0
Field L03[1:0] L02[1:0] L01[1:0] L00[1:0]
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
ILR1
bit 7 6 5 4 3 2 1 0
Field L07[1:0] L06[1:0] L05[1:0] L04[1:0]
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
ILR2
bit 7 6 5 4 3 2 1 0
Field L11[1:0] L10[1:0] L09[1:0] L08[1:0]
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
ILR3
bit 7 6 5 4 3 2 1 0
Field L15[1:0] L14[1:0] L13[1:0] L12[1:0]
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
ILR4
bit 7 6 5 4 3 2 1 0
Field L19[1:0] L18[1:0] L17[1:0] L16[1:0]
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
ILR5
bit 7 6 5 4 3 2 1 0
Field L23[1:0] L22[1:0] L21[1:0] L20[1:0]
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1

Fujitsu 8FX Specifications

General

Brand	Fujitsu
Model	8FX
Category	Computer Hardware
Language	English