Fujitsu 8FX

MB95630H Series
350 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 19 16-BIT PPG TIMER
19.7 Registers
19.7.5 16-bit PPG Status Control Register (Lower) ch. n
(PCNTLn)
The 16-bit PPG status control register (lower) ch. n controls the hardware
trigger, interrupt, output, and output polarity of the 16-bit PPG timer.
■ Register Configuration
■ Register Functions
[bit7] EGS1: Hardware trigger enable bit 1
This bit enables or disables stopping the operation of the 16-bit PPG timer at a falling edge of the TRGn
input.
[bit6] EGS0: Hardware trigger enable bit 0
This bit enables or disables starting the operation of the 16-bit PPG timer at a rising edge of the TRGn input.
[bit5] IREN: PPG interrupt request enable bit
This bit enables or disables making the 16-bit PPG timer interrupt request to the interrupt controller.
[bit4] IRQF: PPG interrupt flag bit
This bit is set to "1" when the 16-bit PPG timer interrupt is generated.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit 7 6 5 4 3 2 1 0
Field EGS1 EGS0 IREN IRQF IRS1 IRS0 POEN OSEL
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
bit7 Details
Writing "0" Disables stopping the operation of the 16-bit PPG timer at a falling edge of the TRGn input.
Writing "1" Enables stopping the operation of the 16-bit PPG timer at a falling edge of the TRGn input.
bit6 Details
Writing "0" Disables starting the operation of the 16-bit PPG timer at a rising edge of the TRGn input.
Writing "1" Enables starting the operation of the 16-bit PPG timer at a rising edge of the TRGn input.
bit5 Details
Writing "0" Disables the 16-bit PPG timer interrupt request.
Writing "1" Enables the 16-bit PPG timer interrupt request.
bit4 Details
Reading "0" Indicates that no 16-bit PPG timer interrupt has been generated.
Reading "1" Indicates that a 16-bit PPG timer interrupt has been generated.
Writing "0" Clears this bit.
Writing "1" Has no effect on operation.