Fujitsu 8FX User Manual

MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 517
CHAPTER 24 I
2
C BUS INTERFACE
24.7 Registers
24.7.2 I
2
C Bus Control Register 1 ch. n (IBCR1n)
The I
2
C bus control register 1 ch. n (IBCR1n) controls the following functions:
bus error interrupt, START condition generation, master/slave mode selection,
data acknowledge, general call acknowledge and transfer completion interrupt.
■ Register Configuration
■ Register Functions
[bit7] BER: Bus error interrupt request flag bit
This bit detects the bus error.
When this bit and the BEIE bit are both set to "1", a bus error interrupt is generated.
This bit is set to "1" when an invalid START condition or an invalid STOP condition is detected.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
When this bit is set to "1", the ICCRn:EN bit is set to "0", and the I
2
C bus interface operation is disabled and
data transfer is terminated.
[bit6] BEIE: Bus error interrupt enable bit
This bit enables or disables the bus error interrupt.
When this bit and the BER bit are both set to "1", a bus error interrupt request is generated.
bit 7 6 5 4 3 2 1 0
Field BER BEIE SCC MSS DACKE GACKE INTE INT
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
bit7 Details
Reading "0" Indicates that no bus error has been detected.
Reading "1" Indicates that an invalid START condition or an invalid STOP condition has been detected.
Writing "0" Clears this bit.
Writing "1" Has no effect on operation.
bit6 Details
Writing "0" Disables the bus error interrupt.
Writing "1" Enables the bus error interrupt.

Fujitsu 8FX Specifications

General

Brand	Fujitsu
Model	8FX
Category	Computer Hardware
Language	English