MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 447
CHAPTER 21 MULTI-PULSE GENERATOR
21.6 Registers
21.6.8 16-bit MPG Timer Control Status Register (TCSR)
The 16-bit MPG timer control status register (TCSR) controls the operation of
the 16-bit timer.
â– Register Configuration
â– Register Functions
[bit7] TCLR: Timer clear bit
The read value of this bit is always "0".
Writing "1" to this bit initializes the counter of the 16-bit timer to "0x0000".
Writing "0" to this bit has no effect on operation.
[bit6] MODE: Timer reset condition bit
This bit sets the reset condition for the 16-bit timer.
Note: The 16-bit timer is reset upon a change in the 16-bit timer value.
[bit5] ICLR: Compare clear interrupt request flag bit
This bit is the compare clear interrupt request flag.
When the value of the 16-bit MPG compare clear register (upper/lower) (CPCUR/CPCLR) match the 16-bit
timer value, the counter of the 16-bit timer is cleared and this bit is set to "1".
With the compare clear interrupt request already enabled (TCSR:ICRE = 1), when the ICLR bit is set to "1",
a compare clear interrupt is generated.
Writing "0" to this bit clears it. Writing "1" to this bit has no effect on operation.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit 7 6 5 4 3 2 1 0
Field TCLR MODE ICLR ICRE TMEN CLK2 CLK1 CLK0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
bit7 Details
Read access The read value is always "0".
Writing "0" Has no effect on operation.
Writing "1" Initializes the counter of the 16-bit timer to "0x0000".
bit6 Details
Writing "0" The 16-bit timer is reset at a write timing signal.
Writing "1" The 16-bit timer is reset at a position detection signal.
bit5 Details
Reading "0" Indicates that no compare clear interrupt request has been generated.
Reading "0" Indicates that a compare clear interrupt request has been generated.
Writing "0" Clears this bit.
Writing "1" Has no effect on operation.
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