MB95630H Series
72 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 5 INTERRUPTS
5.1 Interrupts
5.1 Interrupts
This section describes the interrupts.
â– Overview of Interrupts
The New 8FX family has 24 interrupt request inputs for respective peripheral functions, for
each of which an interrupt level can be set independently to each other.
When a peripheral function generates an interrupt request, the interrupt request is output to the
interrupt controller. The interrupt controller checks the interrupt level of that interrupt request
and then notifies the CPU of the generation of the interrupt. The CPU processes that interrupt
according to the interrupt acceptance status. The device wakes up from standby mode by an
interrupt request generated in standby mode and resumes executing instructions.
â– Interrupt Requests from Peripheral Functions
When the CPU receives an interrupt request, it branches to the interrupt service routine with
the interrupt vector table address corresponding to the interrupt request as the address of the
branch destination.
The priority of each interrupt request in interrupt processing can be set to one of the four levels
by the interrupt level setting registers (ILR0 to ILR5).
While an interrupt is being processed in the interrupt service routine, if another interrupt whose
interrupt request is of the same level or below the one of the interrupt being processed is
generated, it is processed after the current interrupt service routine is completed. In addition, if
multiple interrupt requests that are set to the same interrupt level are made, IRQ00 is at the top
of the priority order.
For interrupt sources, refer to "â– INTERRUPT SOURCE TABLE" in the device data sheet.
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