MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 421
CHAPTER 21 MULTI-PULSE GENERATOR
21.5 Operations
21.5.7 Operation of 16-bit Timer
The 16-bit timer has a buffer and compare clear function, which is used for
motor speed checking and abnormal detection timeout. The 16-bit timer starts
counting up from counter value "0x0000" after a reset has been completed and
counting enable bit is set.
■ 16-bit Timer Operation
The counter value is cleared in the following conditions:
• When an overflow has occurred.
• When a match with the 16-bit MPG compare clear register (upper/lower) (CPCUR/CPCLR)
is detected.
• When "1" is written to the TCLR bit in the TCSR register during operation.
• When a write timing signal is generated and MODE bit in TCSR is "0".
• When a position detection signal is generated and MODE bit in TCSR is "1".
•Reset
An interrupt can be generated when the counter is cleared due to a match with the compare
clear register. There is no interrupt when an overflow occurs.
Note:
To access the compare clear register and the timer buffer register, the word access
instruction must be used.
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