MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 323
CHAPTER 18 8/16-BIT PPG
18.7 Registers
18.7.2 8/16-bit PPG timer n0 Control Register (PCn0)
The 8/16-bit PPG timer n0 control register (PCn0) sets the operating conditions
and the operation mode for PPG timer n0.
â– Register Configuration
â– Register Functions
[bit7:6] MD[1:0]: Operating mode bits
These bits select the PPG operation mode.
Do not modify the settings of these bits during counting.
[bit5] PIE0: Interrupt request enable bit
This bit controls interrupts of PPG timer n0.
In 16-bit PPG mode, use this bit to control the interrupt request of the 8/16-bit PPG.
The bit outputs an interrupt request (IRQ) when the counter borrow detection bit (PUF0) and the PIE0 bit are
both set to "1".
[bit4] PUF
0: Counter borrow detection flag bit for PPG cycle downcounter
This bit serves as the counter borrow detection flag for the PPG cycle downcounter of the PPG timer n0.
In 16-bit PPG mode, only this bit is effective and the PUF1 bit in the PCn1 register has no effect on
operation.
Note: In 8-bit PPG independent mode or 8-bit prescaler + 8-bit PPG mode, counter borrow detection is
always enabled.
Writing "1" to this bit has no effect on operation. Writing "0" to this bit clears it.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit 7 6 5 4 3 2 1 0
Field MD1 MD0 PIE0 PUF0 POEN0 CKS02 CKS01 CKS00
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
bit7:6 Details
Writing "00" 8-bit PPG independent mode
Writing "01" 8-bit prescaler + 8-bit PPG mode
Writing "10"
16-bit PPG mode
Writing "11"
bit5 Details
Writing "0" Disables the PPG timer n0 interrupt.
Writing "1" Enables the PPG timer n0 interrupt.
bit4 Details
Reading "0" Indicates that no counter borrow of PPG timer n0 has been detected.
Reading "1" Indicates that a counter borrow of PPG timer n0 has been detected.
Writing "0" Clears this bit.
Writing "1" Has no effect on operation.
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