Fujitsu 8FX

MB95630H Series
322 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 18 8/16-BIT PPG
18.7 Registers
[bit2:0] CKS1[2:0]: Operating clock select bits
These bits select the operating clock for 8-bit downcounter of the PPG timer n1.
The operating clock is generated from the prescaler. For details, see "3.9 Operation of Prescaler".
In 16-bit PPG mode, the settings of these bits have no effect on the operation.
Note: In subclock mode or sub-CR clock mode, since the time-base timer stops operating, setting CKS1[2:0]
to "0b110" or "0b111" is prohibited.
bit2:0
Details
(MCLK: machine clock, F
CH
: main clock,
F
CRH
: main CR clock, F
MCRPLL
: main CR PLL clock)
Writing "000" 1 MCLK
Writing "001" MCLK/2
Writing "010" MCLK/4
Writing "011" MCLK/8
Writing "100" MCLK/16
Writing "101" MCLK/32
Writing "110"
F
CH
/2
7
or F
CRH
/2
6
or F
MCRPLL
/2
6
Writing "111"
F
CH
/2
8
or F
CRH
/2
7
or F
MCRPLL
/2
7