Fujitsu 8FX

MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 101
CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER
8.2 Configuration
8.2 Configuration
The watchdog timer consists of the following blocks:
• Count clock selector
• Watchdog timer counter
• Reset control circuit
• Watchdog timer clear selector
• Counter clear control circuit
• Watchdog timer control register (WDTC)
■ Block Diagram of Watchdog Timer
Figure 8.2-1 Block Diagram of Watchdog Timer
CS0 CSP WTE3 WTE2 WTE0WTE1
Count clock
selector
Watchdog timer
clear selector
Counter clear
control circuit
Reset
control
circuit
Reset
signal
Clear signal from
time-base timer
Clear signal from
watch prescaler
Sleep mode starts
Stop mode starts
Time-base timer/watch mode starts
F
CH
FCL
2
14
/FCL (or 2
13
/FCRL),
2
13
/FCL (or 2
12
/FCRL)
(Watch prescaler output)
2
21
/FCH (or 2
20
/FCRH or 2
20
/FMCRPLL),
2
20
/FCH (or 2
19
/FCRH or 2
19
/FMCRPLL)
(Time-base timer output)
Watchdog
timer counter
Overflow
Watchdog timer
ActivateClear
Watchdog timer control register (WDTC)
CS1
HWWDT
2
16
/FCRL
(Sub-CR timer)
F
CRL
: Main clock
F
CRH : Main CR clock
F
MCRPLL : Main CR PLL clock
: Subclock
: Sub-CR clock
Stopping or running in stop mode