Fujitsu 8FX User Manual

MB95630H Series
524 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 24 I
2
C BUS INTERFACE
24.7 Registers
24.7.4 I
2
C Data Register ch. n (IDDRn)
The I
2
C data register ch. n (IDDRn) sets the data or address to be transmitted,
and holds the data or address received.
■ Register Configuration
■ Register Functions
In transmit mode, each bit of the data or address value written to the register is shifted to the
SDAn line, starting with the MSB. The write side of this register is double-buffered, where if
the bus is in use (IBSRn:BB = 1), the write data is loaded to the 8-bit shift register either when
the current data transfer completion interrupt is cleared (writing "0" to the IBCR1n:INT bit) or
when a repeated start condition is generated (writing "1" to the IBCR1n:SCC bit). Each bit of
the shift register data is output (shifted) to the SDAn line.
Note that writing to this register has no effect on the current data transfer. In slave mode,
however, data is transferred to the shift register after the address is determined.
The received data or address can be read from this register at the transfer completion interrupt
(IBCR1n:INT = 1). However, since the serial transfer register is directly read from when the
received data or address is read, the receive data is valid only when the INT bit is "1".
bit 7 6 5 4 3 2 1 0
Field D7 D6 D5 D4 D3 D2 D1 D0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0

Fujitsu 8FX Specifications

General

Brand	Fujitsu
Model	8FX
Category	Computer Hardware
Language	English