Fujitsu 8FX

MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 495
CHAPTER 24 I
2
C BUS INTERFACE
24.2 Configuration
24.2 Configuration
The I
2
C bus interface consists of the following blocks:
• Clock selector
• Clock divider
• Shift clock generator
• Start/stop condition generation circuit
• Start/stop condition detection circuit
• Arbitration lost detection circuit
• Slave address comparison circuit
• IBSRn register
• IBCR0n register
• IBCR1n register
• ICCRn register
• IAARn register
• IDDRn register
The number of pins and that of channels of the I
2
C bus interface vary among products. For
details, refer to the device data sheet.
In this chapter, "n" in a pin name and a register abbreviation represents the channel number.
For details of pin names, register names and register abbreviations of a product, refer to the
device data sheet.