Fujitsu 8FX

MB95630H Series
374 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 20 16-BIT RELOAD TIMER
20.7 Registers
20.7.3 16-bit Reload Timer Timer Register (Upper/Lower)
ch. n (TMRHn/TMRLn)
The 16-bit reload timer timer register (upper/lower) ch. n (TMRHn/TMRLn) reads
the count value of the 16-bit downcounter.
■ Register Configuration
■ Register Functions
The 16-bit reload timer timer register ch. n reads the count value of the 16-bit downcounter.
If the counting operation has already been enabled (TMCSRLn:CNTE = 1) when the 16-bit
reload timer starts counting, the value set to the 16-bit reload timer reload register is reloaded
to the 16-bit reload timer timer register ch. n, and then the 16-bit reload timer starts
downcounting.
Notes:
• This register can read the count value even during the counting operation of the 16-bit
reload timer. To read this register, use a word transfer instruction, or read the upper
byte of this register first and then its lower byte. The circuit of the 16-bit reload timer
timer register ch. n is configured so that the lower byte value is saved when the upper
byte value is read.
• This register is read-only and located at the same address as the 16-bit reload timer
reload register ch. n. Therefore, a write access to this register becomes a write access
to the 16-bit reload timer reload register ch. n.
TMRHn
bit 7 6 5 4 3 2 1 0
Field D15 D14 D13 D12 D11 D10 D9 D8
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
TMRLn
bit 7 6 5 4 3 2 1 0
Field D7 D6 D5 D4 D3 D2 D1 D0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0