MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 339
CHAPTER 19 16-BIT PPG TIMER
19.5 Interrupts
19.5 Interrupts
The 16-bit PPG timer can generate interrupt requests in the following cases:
• When a trigger or counter borrow occurs
• When a rising edge of PPG is generated in normal polarity
• When a falling edge of PPG is generated in inverted polarity
The interrupt operation is controlled by the IRS[1:0] bits in the PCNTLn register.
■ Interrupts of 16-bit PPG Timer
Table 19.5-1 shows interrupt control bits and interrupt sources of the 16-bit PPG timer.
When the IRQF bit in the 16-bit PPG status control register (PCNTLn) is set to "1" and
interrupt requests are enabled (PCNTLn:IREN = 1) in the 16-bit PPG timer, an interrupt
request is generated and output to the controller.
Table 19.5-1 Interrupt Control Bits and Interrupt Sources of 16-bit PPG Timer
Item Description
Interrupt flag bit PCNTLn:IRQF
Interrupt request enable bit PCNTLn:IREN
Interrupt type select bits PCNTLn:IRS[1:0]
Interrupt sources
PCNTLn:IRS[1:0] = 0b00
Hardware trigger by TRGn pin input of 16-bit downcounter, software
trigger and retrigger
PCNTLn:IRS[1:0] = 0b01
Counter borrow of 16-bit downcounter
PCNTLn:IRS[1:0] = 0b10
Rising edge of PPGn output in normal polarity, or falling edge of PPGn
output in inverted polarity
PCNTLn:IRS[1:0] = 0b11
Counter borrow of 16-bit downcounter, rising edge of PPGn output in
normal polarity, or falling edge of PPGn output in inverted polarity
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