Fujitsu 8FX User Manual

MB95630H Series
448 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 21 MULTI-PULSE GENERATOR
21.6 Registers
[bit4] ICRE: Compare clear interrupt enable bit
This bit enables or disables the compare clear interrupt.
When this bit is set to "1", and the compare clear interrupt request flag bit (ICLR) is also set to "1", a
compare clear interrupt is generated.
[bit3] TMEN: Timer enable bit
This bit enables or disables the counting operation of the 16-bit timer.
Note: When the counting operation of the 16-bit timer is disabled, the output compare operation is also
disabled.
[bit2:0] CLK[2:0]: Clock frequency select bits
These bits select the count clock of the 16-bit timer.
Note: Since the count clock is changed immediately after these bits are updated, it is recommend to modify
these bits while the 16-bit timer is in stop state.
bit4 Details
Writing "0" Disables the compare clear interrupt.
Writing "1" Enables the compare clear interrupt.
bit3 Details
Writing "0" Disables the counting operation of the 16-bit timer.
Writing "1" Enables the counting operation of the 16-bit timer.
bit2:0
Details
(MCLK: machine clock)
Count clock MCLK = 16 MHz MCLK = 8 MHz MCLK = 4 MHz MCLK = 1 MHz
Writing "000" 1 MCLK 62.5 ns 125 ns 0.25 µs 1 µs
Writing "001" MCLK/2 125 ns 0.25 µs 0.5 µs 2 µs
Writing "010" MCLK/4 0.25 µs 0.5 µs 1 µs 4 µs
Writing "011" MCLK/8 0.5 µs 1 µs 2 µs 8 µs
Writing "100" MCLK/16 1 µs 2 µs 4 µs 16 µs
Writing "101" MCLK/32 2 µs 4 µs 8 µs 32 µs
Writing "110" MCLK/64 4 µs 8 µs 16 µs 64 µs
Writing "111" MCLK/128 8 µs 16 µs 32 µs 128 µs

Fujitsu 8FX Specifications

General

Brand	Fujitsu
Model	8FX
Category	Computer Hardware
Language	English