MB95630H Series
162 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 11 8/16-BIT COMPOSITE TIMER
11.14 Registers
[bit3:0] F[3:0]: Timer operating mode select bits
These bits select the timer operating mode.
The PWM timer function (variable-cycle mode; F[3:0] = 0b0100) is set by either the Tn0CR0 (timer n0)
register or Tn1CR0 (timer n1) register. If one of the timers starts operating (Tn0CR1/Tn1CR1: STA= 1), the
F[3:0] bits of the other timer are automatically set to "0b0100".
With the 16-bit operation having been selected (TMCRn:MOD = 1), if the composite timer starts operating
using the PWM timer function (variable-cycle mode) (Tn0CR1/Tn1CR1:STA = 1), the MOD bit is set to "0"
automatically.
Write access to these bits is nullified in timer operation (Tn0CR1/Tn1CR1:STA = 1).
bit3:0 Details
Writing "0000" Interval timer (one-shot mode)
Writing "0001" Interval timer (continuous mode)
Writing "0010" Interval timer (free-run mode)
Writing "0011" PWM timer (fixed-cycle mode)
Writing "0100" PWM timer (variable-cycle mode)
Writing "0101" PWC timer (H pulse = rising edge to falling edge)
Writing "0110" PWC timer (L pulse = falling edge to rising edge)
Writing "0111" PWC timer (cycle = rising edge to rising edge)
Writing "1000" PWC timer (cycle = falling edge to falling edge)
Writing "1001" PWC timer (H pulse = rising edge to falling edge; cycle = rising edge to rising edge)
Writing "1010" Input capture (rising edge, free-run counter)
Writing "1011" Input capture (falling edge, free-run counter)
Writing "1100" Input capture (both edges, free-run counter)
Writing "1101" Input capture (rising edge, counter clear)
Writing "1110" Input capture (falling edge, counter clear)
Writing "1111" Input capture (both edges, counter clear)
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