MB95630H Series
212 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 14 LIN-UART
14.4 Interrupts
■ Transmit Interrupt Request Generation Timing
With the transmit interrupt having been enabled (SSR:TIE = 1), if the TDRE bit is set to "1", a
transmit interrupt is generated.
Note:
Since the initial value of the TDRE bit is "1", a transmit interrupt is generated immediately
after the transmit interrupt is enabled (SSR:TIE = 1). When deciding the timing of
enabling the transmit interrupt, take into consideration that the TDRE bit can be cleared
only by writing new data to the LIN-UART transmit data register (TDR).
For interrupt request numbers and vector table addresses of respective peripheral functions,
refer to "■ INTERRUPT SOURCE TABLE" in the device data sheet.
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