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Fujitsu 8FX User Manual
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MB95630H Series
MN702-00009-2v0
-E
FUJITSU SEMICONDUCT
OR LIMITED
261
CHAPTER 14 LIN-UAR
T
14.8 Notes on Using LIN-U
AR
T
Figure
14.8-1
U
ART Dominant
Bus Operation
When reception i
s
a
lw
a
y
s
en
ab
led (RXE = 1)
When reception i
s
tempor
a
rily di
sab
led (RXE = 1
→
0
→
1)
Fr
a
ming error
occ
u
r
s
Error i
s
cle
a
red
Reception i
s
ongoing
reg
a
rdre
ss
of no f
a
lling
edge
F
a
lling edge i
s
next
s
t
a
rt
b
it
edge
Next fr
a
ming
error occ
u
r
s
Fr
a
ming error
occ
u
r
s
Error i
s
cle
a
red
F
a
lling edge i
s
next
s
t
a
rt
b
it
edge
Reception i
s
ongoing
reg
a
rdre
ss
of no f
a
lling
edge
No f
u
rther error
s
S
IN
FRE
CRE
RXE
S
IN
FRE
CRE
Reception i
s
re
s
et:
W
a
itng for f
a
lling edge
282
284
Table of Contents
Default Chapter
9
Table of Contents
9
Chapter 1 Memory Access Mode
23
Memory Access Mode
24
Chapter 2 Cpu
25
Dedicated Registers
26
Register Bank Pointer (RP)
28
Direct Bank Pointer (DP)
29
Condition Code Register (CCR)
31
General-Purpose Register
33
Placement of 16-Bit Data in Memory
35
Chapter 3 Clock Controller
37
Overview
38
Oscillation Stabilization Wait Time
46
Registers
49
System Clock Control Register (SYCC)
50
PLL Control Register (PLLC)
51
Oscillation Stabilization Wait Time Setting Register (WATR)
52
Standby Control Register (STBC)
54
System Clock Control Register 2 (SYCC2)
56
Standby Control Register 2 (STBC2)
58
Clock Modes
59
Operations in Low Power Consumption Mode (Standby Mode)
63
Notes on Using Standby Mode
64
Sleep Mode
70
Stop Mode
71
Time-Base Timer Mode
73
Watch Mode
75
Clock Oscillator Circuit
76
Overview of Prescaler
77
Configuration of Prescaler
78
Operation of Prescaler
79
Notes on Using Prescaler
81
Chapter 4 Reset
83
Reset Operation
84
Register
88
Reset Source Register (RSRR)
89
Notes on Using Reset
92
Chapter 5 Interrupts
93
Interrupts
94
Interrupt Level Setting Registers (ILR0 to ILR5)
95
Interrupt Processing
97
Nested Interrupts
99
Interrupt Processing Time
100
Stack Operation During Interrupt Processing
101
Interrupt Processing Stack Area
102
Chapter 6 I/O Port
103
Overview
104
Configuration and Operations
105
Chapter 7 Time-Base Timer
109
Overview
110
Configuration
111
Interrupt
113
Operations and Setting Procedure Example
114
Register
117
Time-Base Timer Control Register (TBTC)
118
Notes on Using Time-Base Timer
120
Chapter 8 Hardware/Software Watchdog Timer
121
Overview
122
Configuration
123
Operations and Setting Procedure Example
125
Register
128
Watchdog Timer Control Register (WDTC)
129
Notes on Using Watchdog Timer
131
Chapter 9 Watch Prescaler
133
Overview
134
Configuration
135
Interrupt
137
Operations and Setting Procedure Example
138
Register
141
Watch Prescaler Control Register (WPCR)
142
Notes on Using Watch Prescaler
144
Chapter 10 Wild Register Function
145
Overview
146
Configuration
147
Operations
149
Registers
150
Wild Register Data Setting Registers (WRDR0 to WRDR2)
151
Wild Register Address Setting Registers (WRAR0 to WRAR2)
152
Wild Register Address Compare Enable Register (WREN)
153
Wild Register Data Test Setting Register (WROR)
154
Typical Hardware Connection Example
155
Chapter 11 8/16-Bit Composite Timer
157
Overview
158
Configuration
160
Channel
163
Pins
164
Interrupts
165
Operation of Interval Timer Function (One-Shot Mode)
166
Operation of Interval Timer Function (Continuous Mode)
168
Operation of Interval Timer Function (Free-Run Mode)
170
Operation of PWM Timer Function (Fixed-Cycle Mode)
172
Operation of PWM Timer Function (Variable-Cycle Mode)
174
11.11 Operation of PWC Timer Function
176
11.12 Operation of Input Capture Function
178
11.13 Operation of Noise Filter
180
11.14 Registers
181
8/16-Bit Composite Timer Status Control Register 0 (Tn0Cr0/Tn1Cr0)
182
8/16-Bit Composite Timer Status Control Register 1 (Tn0Cr1/Tn1Cr1)
185
8/16-Bit Composite Timer Timer Mode Control Register (Tmcrn)
189
8/16-Bit Composite Timer Data Register (Tn0Dr/Tn1Dr)
192
11.15 Notes on Using 8/16-Bit Composite Timer
195
Chapter 12 External Interrupt Circuit
197
Overview
198
Configuration
199
Channels
200
Pin
201
Interrupt
202
Operations and Setting Procedure Example
203
Register
205
External Interrupt Control Register (EIC)
206
Notes on Using External Interrupt Circuit
208
Chapter 13 Interrupt Pin Selection Circuit
209
Overview
210
Configuration
211
Pins
212
Operation
213
Register
214
Interrupt Pin Selection Circuit Control Register (WICR)
215
Notes on Using Interrupt Pin Selection Circuit
218
Chapter 14 Lin-Uart
219
Overview
220
Configuration
222
Reload Counter
223
Pins
227
Interrupts
228
Timing of Receive Interrupt Generation and Flag Set
231
Timing of Transmit Interrupt Generation and Flag Set
233
LIN-UART Baud Rate
235
Baud Rate Setting
237
Reload Counter
241
Operations of LIN-UART and LIN-UART Setting Procedure Example
243
Operations in Asynchronous Mode (Operating Mode 0, 1)
245
Operations in Synchronous Mode (Operating Mode 2)
249
Operations of LIN Function (Operating Mode 3)
253
Serial Pin Direct Access
256
Bidirectional Communication Function (Normal Mode)
257
Master/Slave Mode Communication Function (Multiprocessor Mode)
259
LIN Communication Function
262
Examples of LIN-UART LIN Communication Flow Chart (Operating Mode 3)
263
Registers
265
LIN-UART Serial Control Register (SCR)
266
LIN-UART Serial Mode Register (SMR)
268
LIN-UART Serial Status Register (SSR)
270
LIN-UART Receive Data Register/Lin-UART Transmit Data Register (RDR/TDR)
272
LIN-UART Extended Status Control Register (ESCR)
274
LIN-UART Extended Communication Control Register (ECCR)
277
LIN-UART Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
279
Notes on Using LIN-UART
280
Chapter 15 8/10-Bit A/D Converter
286
Overview
286
Configuration
287
Pin
289
Interrupt
290
Operations and Setting Procedure Example
291
Registers
294
8/10-Bit A/D Converter Control Register 1 (ADC1)
295
8/10-Bit A/D Converter Control Register 2 (ADC2)
297
8/10-Bit A/D Converter Data Register (Upper/Lower) (ADDH/ADDL)
299
Notes on Using 8/10-Bit A/D Converter
300
Chapter 16 Low-Voltage Detection Reset Circuit
303
Overview
304
Configuration
305
Pins
306
Operation
307
Register
308
LVD Reset Voltage Selection ID Register (LVDR)
309
Chapter 17 Clock Supervisor Counter
311
Overview
312
Configuration
313
Operations
315
Registers
320
Clock Monitoring Data Register (CMDR)
321
Clock Monitoring Control Register (CMCR)
322
Notes on Using Clock Supervisor Counter
324
Chapter 18 8/16-Bit Ppg
327
Overview
328
Configuration
329
Channel
331
Pins
332
Interrupt
333
Operations and Setting Procedure Example
334
8-Bit PPG Independent Mode
335
8-Bit Prescaler + 8-Bit PPG Mode
337
16-Bit PPG Mode
339
Registers
342
8/16-Bit PPG Timer N1 Control Register (Pcn1)
343
8/16-Bit PPG Timer N0 Control Register (Pcn0)
345
8/16-Bit PPG Timer N1/N0 Cycle Setup Buffer Register (Ppsn1/Ppsn0)
347
8/16-Bit PPG Timer N1/N0 Duty Setup Buffer Register (Pdsn1/Pdsn0)
348
8/16-Bit PPG Start Register (PPGS)
349
8/16-Bit PPG Output Reverse Register (REVC)
351
Notes on Using 8/16-Bit PPG
353
Chapter 19 16-Bit Ppg Timer
355
Overview
356
Configuration
357
Channel
359
Pins
360
Interrupts
361
Operations and Setting Procedure Example
362
Registers
366
16-Bit PPG Downcounter Register (Upper/Lower) Ch. N (Pdcrhn/Pdcrln)
367
16-Bit PPG Cycle Setting Buffer Register (Upper/ Lower) Ch. N (Pcsrhn/Pcsrln)
368
16-Bit PPG Duty Setting Buffer Register (Upper/Lower) Ch. N (Pduthn/Pdutln)
369
16-Bit PPG Status Control Register (Upper) Ch. N (Pcnthn)
370
16-Bit PPG Status Control Register (Lower) Ch. N (Pcntln)
372
Notes on Using 16-Bit PPG Timer
374
Chapter 20 16-Bit Reload Timer
375
Overview
376
Configuration
378
Channel
380
Pins
381
Interrupt
382
Operations and Setting Procedure Example
383
Internal Clock Mode
385
Event Count Mode
389
Registers
391
16-Bit Reload Timer Control Status Register (Upper) Ch. N (Tmcsrhn)
392
16-Bit Reload Timer Control Status Register (Lower) Ch. N (Tmcsrln)
394
16-Bit Reload Timer Timer Register (Upper/Lower) Ch. N (Tmrhn/Tmrln)
396
16-Bit Reload Timer Reload Register (Upper/Lower) Ch. N (Tmrlrhn/Tmrlrln)
397
Notes on Using 16-Bit Reload Timer
398
Chapter 21 Multi-Pulse Generator
399
Overview
400
Block Diagram
403
Pins
411
Interrupts
412
Operations
414
Operation of Position Detection
416
Operation of Data Write Control Unit
418
Operation of 16-Bit MPG Output Data Buffer Register (Upper/Lower) (Opdbrhx/Opdbrlx)
422
Operation of Data Transfer of 16-Bit MPG Output Data Register (Upper/Lower)
424
At OPDBRH0 and OPDBRL0 Write
426
At 16-Bit Reload Timer Underflow
427
At Position Detection
429
At Position Detection and Timer Underflow
431
At Position Detection or Timer Underflow
434
At One-Shot Position Detection
436
When One-Shot Position Detection and Reload Timer Underflow
437
When One-Shot Position Detection or Reload Timer Underflow
438
Operation of DTTI Input Control
439
Operation of Noise Cancellation Function
442
Operation of 16-Bit Timer
443
Registers
448
16-Bit MPG Output Control Register (Upper) (OPCUR)
449
16-Bit MPG Output Control Register (Lower) (OPCLR)
451
16-Bit MPG Output Data Register (Upper/Lower) (OPDUR/OPDLR)
453
16-Bit MPG Output Data Register (Upper) (OPDUR)
454
16-Bit MPG Output Data Register (Lower) (OPDLR)
456
16-Bit MPG Output Data Buffer Register (Upper/Lower) (Opdbrhx/Opdbrlx)
457
16-Bit MPG Output Data Buffer Register (Upper) (Opdbrhx)
458
16-Bit MPG Output Data Buffer Register (Lower) (Opdbrlx)
460
16-Bit MPG Input Control Register (Upper/Lower) (IPCUR/IPCLR)
462
16-Bit MPG Input Control Register (Upper) (IPCUR)
463
16-Bit MPG Input Control Register (Lower) (IPCLR)
465
16-Bit MPG Compare Clear Register (Upper/Lower) (CPCUR/CPCLR)
467
16-Bit MPG Timer Buffer Register (Upper/Lower) (TMBUR/TMBLR)
468
16-Bit MPG Timer Control Status Register (TCSR)
469
16-Bit MPG Noise Cancellation Control Register (NCCR)
471
Notes on Using Multi-Pulse Generator
472
Sample Program for Multi-Pulse Generator
474
Chapter 22 Uart/Sio
477
Overview
478
Configuration
479
Channel
481
Pins
482
Interrupts
483
Operations and Setting Procedure Example
484
Operations in Operation Mode 0
485
Operations in Operation Mode 1
492
Registers
498
UART/SIO Serial Mode Control Register 1 Ch. N (Smc1N)
499
UART/SIO Serial Mode Control Register 2 Ch. N (Smc2N)
501
UART/SIO Serial Status and Data Register Ch. N (Ssrn)
503
UART/SIO Serial Input Data Register Ch. N (Rdrn)
505
UART/SIO Serial Output Data Register Ch. N (Tdrn)
506
Chapter 23 Uart/Sio Dedicated Baud Rate Generator
507
Overview
508
Channel
509
Operations
510
Registers
511
UART/SIO Dedicated Baud Rate Generator Prescaler Select Register Ch. N (Pssrn)
512
UART/SIO Dedicated Baud Rate Generator Baud Rate Setting Register Ch. N (Brsrn)
513
Chapter 24 I 2 C Bus Interface
515
Overview
516
Configuration
517
Channel
520
Pins
521
Interrupts
522
Operations and Setting Procedure Example
524
C Bus Interface
525
Function to Wake up the MCU from Standby Mode
533
Registers
535
I 2 C Bus Control Register 0 Ch. N (Ibcr0N)
536
C Bus Control Register 1 Ch. N (Ibcr1N)
539
I 2 C Bus Status Register Ch. N (Ibsrn)
543
I 2 C Data Register Ch. N (Iddrn)
546
I 2 C Address Register Ch. N (Iaarn)
547
I 2 C Clock Control Register Ch. N (Iccrn)
548
Notes on Using I 2 C Bus Interface
550
Chapter 25 Example of Serial Programming Connection
553
Basic Configuration of Serial Programming Connection
554
Example of Serial Programming Connection
555
Chapter 26 Dual Operation Flash Memory
557
Overview
558
Sector/Bank Configuration
560
Invoking Flash Memory Automatic Algorithm
561
Checking Automatic Algorithm Execution Status
563
Data Polling Flag (DQ7)
565
Toggle Bit Flag (DQ6)
567
Execution Timeout Flag (DQ5)
568
Sector Erase Timer Flag (DQ3)
569
Toggle Bit2 Flag (DQ2)
570
Programming/Erasing Flash Memory
571
Placing Flash Memory in Read/Reset State
572
Programming Data to Flash Memory
573
Erasing All Data from Flash Memory (Chip Erase)
575
Erasing Specific Data from Flash Memory (Sector Erase)
576
Suspending Sector Erase from Flash Memory
578
Resuming Sector Erase of Flash Memory
579
Unlock Bypass Program
580
Operations
581
Flash Security
583
Registers
584
Flash Memory Status Register 2 (FSR2)
585
Flash Memory Status Register (FSR)
588
Flash Memory Sector Write Control Register 0 (SWRE0)
591
Flash Memory Status Register 3 (FSR3)
593
Flash Memory Status Register 4 (FSR4)
594
Notes on Using Dual Operation Flash Memory
602
Chapter 27 Non-Volatile Register (Nvr) Interface
603
Overview
604
Configuration
605
Registers
606
Main CR Clock Trimming Register (Upper) (CRTH)
607
Main CR Clock Trimming Register (Lower) (CRTL)
608
Main CR Clock Temperature Dependent Adjustment Register (CRTDA)
609
Watchdog Timer Selection ID Register (Upper/Lower) (WDTH/WDTL)
610
Notes on Main CR Clock Trimming
611
Notes on Using NVR Interface
613
Chapter 28 Comparator
615
Overview
616
Configuration
617
Pins
619
Interrupt
620
Operations and Setting Procedure Example
621
Register
622
Comparator Control Register (CMR0C)
623
Chapter 29 System Configuration Controller
625
Overview
626
Register
627
System Configuration Register (SYSC)
628
Notes on Using Controller
630
Appendix
631
APPENDIX A Instruction Overview
632
Addressing
635
A.1 Addressing
635
Special Instruction
639
A.2 Special Instruction
639
APPENDIX A Instruction Overview
647
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Fujitsu 8FX Specifications
General
Brand
Fujitsu
Model
8FX
Category
Computer Hardware
Language
English
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