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MB95630H Series

MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 261

CHAPTER 14 LIN-UART

14.8 Notes on Using LIN-UART

Figure 14.8-1 UART Dominant Bus Operation

When reception is always enabled (RXE = 1)

When reception is temporarily disabled (RXE = 1 → 0 → 1)

Framing error

occurs

Error is

cleared

Reception is ongoing

regardress of no falling

edge

Falling edge is

next start bit

edge

Next framing

error occurs

Framing error

occurs

Error is cleared

Falling edge is

next start bit

edge

Reception is ongoing

regardress of no falling

edge

No further errors

SIN

FRE

CRE

RXE

SIN

FRE

CRE

Reception is reset:

Waitng for falling edge

Main Page

Default Chapter9
- Table of Contents9
Chapter 1 Memory Access Mode23
- Memory Access Mode24
Chapter 2 Cpu25
- Dedicated Registers26
- General-Purpose Register33
- Placement of 16-Bit Data in Memory35
Chapter 3 Clock Controller37
- Overview38
- Oscillation Stabilization Wait Time46
- Registers49
- Clock Modes59
- Operations in Low Power Consumption Mode (Standby Mode)63
- Clock Oscillator Circuit76
- Overview of Prescaler77
- Configuration of Prescaler78
- Operation of Prescaler79
- Notes on Using Prescaler81
Chapter 4 Reset83
- Reset Operation84
- Register88
  - Reset Source Register (RSRR)89
- Notes on Using Reset92
Chapter 5 Interrupts93
- Interrupts94
Chapter 6 I/O Port103
- Overview104
- Configuration and Operations105
Chapter 7 Time-Base Timer109
- Overview110
- Configuration111
- Interrupt113
- Operations and Setting Procedure Example114
- Register117
  - Time-Base Timer Control Register (TBTC)118
- Notes on Using Time-Base Timer120
Chapter 8 Hardware/Software Watchdog Timer121
- Overview122
- Configuration123
- Operations and Setting Procedure Example125
- Register128
  - Watchdog Timer Control Register (WDTC)129
- Notes on Using Watchdog Timer131
Chapter 9 Watch Prescaler133
- Overview134
- Configuration135
- Interrupt137
- Operations and Setting Procedure Example138
- Register141
  - Watch Prescaler Control Register (WPCR)142
- Notes on Using Watch Prescaler144
Chapter 10 Wild Register Function145
- Overview146
- Configuration147
- Operations149
- Registers150
- Typical Hardware Connection Example155
Chapter 11 8/16-Bit Composite Timer157
- Overview158
- Configuration160
- Channel163
- Pins164
- Interrupts165
- Operation of Interval Timer Function (One-Shot Mode)166
- Operation of Interval Timer Function (Continuous Mode)168
- Operation of Interval Timer Function (Free-Run Mode)170
- Operation of PWM Timer Function (Fixed-Cycle Mode)172
- Operation of PWM Timer Function (Variable-Cycle Mode)174
- 11.11 Operation of PWC Timer Function176
- 11.12 Operation of Input Capture Function178
- 11.13 Operation of Noise Filter180
- 11.14 Registers181
- 11.15 Notes on Using 8/16-Bit Composite Timer195
Chapter 12 External Interrupt Circuit197
- Overview198
- Configuration199
- Channels200
- Pin201
- Interrupt202
- Operations and Setting Procedure Example203
- Register205
  - External Interrupt Control Register (EIC)206
- Notes on Using External Interrupt Circuit208
Chapter 13 Interrupt Pin Selection Circuit209
- Overview210
- Configuration211
- Pins212
- Operation213
- Register214
  - Interrupt Pin Selection Circuit Control Register (WICR)215
- Notes on Using Interrupt Pin Selection Circuit218
Chapter 14 Lin-Uart219
- Overview220
- Configuration222
- Reload Counter223
- Pins227
- Interrupts228
  - Timing of Receive Interrupt Generation and Flag Set231
  - Timing of Transmit Interrupt Generation and Flag Set233
- LIN-UART Baud Rate235
  - Baud Rate Setting237
  - Reload Counter241
- Operations of LIN-UART and LIN-UART Setting Procedure Example243
- Registers265
- Notes on Using LIN-UART280
Chapter 15 8/10-Bit A/D Converter286
- Overview286
- Configuration287
- Pin289
- Interrupt290
- Operations and Setting Procedure Example291
- Registers294
- Notes on Using 8/10-Bit A/D Converter300
Chapter 16 Low-Voltage Detection Reset Circuit303
- Overview304
- Configuration305
- Pins306
- Operation307
- Register308
  - LVD Reset Voltage Selection ID Register (LVDR)309
Chapter 17 Clock Supervisor Counter311
- Overview312
- Configuration313
- Operations315
- Registers320
  - Clock Monitoring Data Register (CMDR)321
  - Clock Monitoring Control Register (CMCR)322
- Notes on Using Clock Supervisor Counter324
Chapter 18 8/16-Bit Ppg327
- Overview328
- Configuration329
- Channel331
- Pins332
- Interrupt333
- Operations and Setting Procedure Example334
- Registers342
- Notes on Using 8/16-Bit PPG353
Chapter 19 16-Bit Ppg Timer355
- Overview356
- Configuration357
- Channel359
- Pins360
- Interrupts361
- Operations and Setting Procedure Example362
- Registers366
- Notes on Using 16-Bit PPG Timer374
Chapter 20 16-Bit Reload Timer375
- Overview376
- Configuration378
- Channel380
- Pins381
- Interrupt382
- Operations and Setting Procedure Example383
  - Internal Clock Mode385
  - Event Count Mode389
- Registers391
- Notes on Using 16-Bit Reload Timer398
Chapter 21 Multi-Pulse Generator399
- Overview400
- Block Diagram403
- Pins411
- Interrupts412
- Operations414
- Registers448
- Notes on Using Multi-Pulse Generator472
- Sample Program for Multi-Pulse Generator474
Chapter 22 Uart/Sio477
- Overview478
- Configuration479
- Channel481
- Pins482
- Interrupts483
- Operations and Setting Procedure Example484
  - Operations in Operation Mode 0485
  - Operations in Operation Mode 1492
- Registers498
Chapter 23 Uart/Sio Dedicated Baud Rate Generator507
- Overview508
- Channel509
- Operations510
- Registers511
  - UART/SIO Dedicated Baud Rate Generator Prescaler Select Register Ch. N (Pssrn)512
  - UART/SIO Dedicated Baud Rate Generator Baud Rate Setting Register Ch. N (Brsrn)513
Chapter 24 I 2 C Bus Interface515
- Overview516
- Configuration517
- Channel520
- Pins521
- Interrupts522
- Operations and Setting Procedure Example524
  - C Bus Interface525
  - Function to Wake up the MCU from Standby Mode533
- Registers535
- Notes on Using I 2 C Bus Interface550
Chapter 25 Example of Serial Programming Connection553
- Basic Configuration of Serial Programming Connection554
- Example of Serial Programming Connection555
Chapter 26 Dual Operation Flash Memory557
- Overview558
- Sector/Bank Configuration560
- Invoking Flash Memory Automatic Algorithm561
- Checking Automatic Algorithm Execution Status563
- Programming/Erasing Flash Memory571
- Operations581
- Flash Security583
- Registers584
- Notes on Using Dual Operation Flash Memory602
Chapter 27 Non-Volatile Register (Nvr) Interface603
- Overview604
- Configuration605
- Registers606
- Notes on Main CR Clock Trimming611
- Notes on Using NVR Interface613
Chapter 28 Comparator615
- Overview616
- Configuration617
- Pins619
- Interrupt620
- Operations and Setting Procedure Example621
- Register622
  - Comparator Control Register (CMR0C)623
Chapter 29 System Configuration Controller625
- Overview626
- Register627
  - System Configuration Register (SYSC)628
- Notes on Using Controller630
Appendix631
- APPENDIX A Instruction Overview632
APPENDIX A Instruction Overview647

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