MB95630H Series
276 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 15 8/10-BIT A/D CONVERTER
15.6 Registers
[bit3] ADIE: Interrupt request enable bit
This bit enables or disables outputting the interrupt request to the interrupt controller.
When both this bit and the interrupt request flag bit (ADC1: ADI) have been set to "1", an interrupt request is
output.
[bit2] EXT: Continuous start enable bit
This bit selects whether to start the A/D conversion function with the software, or to continuously start the
A/D conversion function whenever a rising edge of the input clock is detected.
[bit1:0] CKDIV[1:0]: Clock select bits
These bits select the clock (CKIN) to be used for A/D conversion. The input clock is generated by the
prescaler. See "3.9 Operation of Prescaler" for details.
The sampling time varies according to the clock selected by these bits.
Modify these bits according to operating conditions (voltage and frequency).
Note: Modify these bits only when the A/D converter has stopped operating.
bit3 Details
Writing "0" Disables outputting the interrupt request.
Writing "1" Enables outputting the interrupt request.
bit2 Details
Writing "0" Starts the A/D conversion function with the AD bit in the ADC1 register.
Writing "1"
Continuously start the A/D conversion function according to the clock selected by the ADCK bit
in the ADC2 register.
bit1:0
Details
(MCLK: machine clock)
Writing "00" 1 MCLK
Writing "01" MCLK/2
Writing "10" MCLK/4
Writing "11" MCLK/8
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