MB95630H Series
292 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-2v0-E
CHAPTER 17 CLOCK SUPERVISOR COUNTER
17.2 Configuration
● Control circuit
This block controls the start and stop of the counter, the counter clock source, and the counter
enable period based on the settings of the clock monitoring control register (CMCR).
● Clock Monitoring Control Register (CMCR)
This register is used to select a counter source clock, select a counter enable period from eight
different time-base timer intervals, start the counter and check whether the counter is operating
or not.
● Clock Monitoring Data Register (CMDR)
This register block is used to read the counter value after the counter stops. The software
determines whether the external clock frequency is correct or not according to the contents of
this register.
● Time-base timer interval selector
This block is used to select the counter enable period from eight different time-base timer
intervals.
● Counter source clock selector
This block is used to select the counter source clock from the main oscillation clock and the
suboscillation clock.
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