Fujitsu 8FX User Manual

MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 301
CHAPTER 17 CLOCK SUPERVISOR COUNTER
17.4 Registers
[bit0] CMCEN: Counter enable bit
This bit enables or disables the clock supervisor counter.
Writing "0" to this bit stops the counter and clears the CMDR register to "0b00000000".
Writing "1" to this bit enables the counter. The counter starts counting when detecting the rising edge of the
time-base timer interval. It stops counting when detecting the second rising edge of the same interval.
This bit is automatically set to "0" when the counter stops.
Notes:
• Do not modify the CMCSEL bit when the CMCEN bit is "1".
• Do not modify the TBTSEL[2:0] bits when the CMCEN bit is "1".
bit0 Details
Writing "0" Disables the counter operation.
Writing "1" Enables the counter operation.

Fujitsu 8FX Specifications

General

Brand	Fujitsu
Model	8FX
Category	Computer Hardware
Language	English