Fujitsu 8FX

MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 341
CHAPTER 19 16-BIT PPG TIMER
19.6 Operations and Setting Procedure Example
● Invalidating the retrigger (RTRG bit in PCNTHn register = 0)
Figure 19.6-1 When Retrigger Is Invalid in PWM Mode
● Validating the retrigger (RTRG bit in PCNTHn register = 1)
Figure 19.6-2 When Retrigger Is Valid in PWM Mode
m
n
0
(1)=n × T ns
(2)=m × T ns
PPG
(1)
(2)
(Normal polarity)
(Inverted polarity)
Time
16-bit downcounter value
Software trigger
n: Value of PDUTH & PDUTL registers
m: Value of PCSRH & PCSRL registers
T : Count clock cycle
Rising edge detected
Trigger ignored
PPG
m
n
0
(1)=n × T ns
(2)=m × T ns
PPG
PPG
(1)
(2)
(Normal polarity)
(Inverted polarity)
Time
Counter value
Software trigger
Rising edge detected
Restarted by trigger
n: Value of PDUTH & PDUTL registers
m: Value of PCSRH & PCSRL registers
T : Count clock cycle